20th International Workshop, LCPC 2007, Urbana, IL, USA, October 11-13, 2007, Revised Selected Papers Herausgegeben:Adve, Vikram; Garzarán, María Jesús; Petersen, Paul
20th International Workshop, LCPC 2007, Urbana, IL, USA, October 11-13, 2007, Revised Selected Papers Herausgegeben:Adve, Vikram; Garzarán, María Jesús; Petersen, Paul
This book constitutes the thoroughly refereed post-conference proceedings of the 20th International Workshop on Languages and Compilers for Parallel Computing, LCPC 2007, held in Urbana, IL, USA, in October 2007. The 23 revised full papers presented were carefully reviewed and selected from 49 submissions. The papers are organized in topical sections on reliability, languages, parallel compiler technology, libraries, run-time systems and performance analysis, and general compiler techniques.
This book constitutes the thoroughly refereed post-conference proceedings of the 20th International Workshop on Languages and Compilers for Parallel Computing, LCPC 2007, held in Urbana, IL, USA, in October 2007. The 23 revised full papers presented were carefully reviewed and selected from 49 submissions. The papers are organized in topical sections on reliability, languages, parallel compiler technology, libraries, run-time systems and performance analysis, and general compiler techniques.Hinweis: Dieser Artikel kann nur an eine deutsche Lieferadresse ausgeliefert werden.
Produktdetails
Produktdetails
Theoretical Computer Science and General Issues 5234
Artikelnr. des Verlages: 12455096, 978-3-540-85260-5
2008
Seitenzahl: 372
Erscheinungstermin: 4. August 2008
Englisch
Abmessung: 235mm x 155mm x 21mm
Gewicht: 569g
ISBN-13: 9783540852605
ISBN-10: 3540852603
Artikelnr.: 24766677
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Inhaltsangabe
Reliability. Compiler Enhanced Incremental Checkpointing. Techniques for Efficient Software Checking. Languages. Revisiting SIMD Programming. Multidimensional Blocking in UPC. An Experimental Evaluation of the New OpenMP Tasking Model. Language Extensions in Support of Compiler Parallelization. Parallel Compiler Technology I. Concurrency Analysis for Shared Memory Programs with Textually Unaligned Barriers. Iteration Disambiguation for Parallelism Identification in Time Sliced Applications. A Novel Asynchronous Software Cache Implementation for the Cell BE Processor. Pillar: A Parallel Implementation Language. Associative Parallel Containers in STAPL. Explicit Dependence Metadata in an Active Visual Effects Library. Supporting Huge Address Spaces in a Virtual Machine for Java on a Cluster. Modeling Relations between Inputs and Dynamic Behavior for General Programs. Evaluation of RDMA Opportunities in an Object Oriented DSM. Automatic Communication Performance Debugging in PGAS Languages. Parallel Compiler Technology II. Exploiting SIMD Parallelism with the CGiS Compiler Framework. Critical Block Scheduling: A Thread Level Parallelizing Mechanism for a Heterogeneous Chip Multiprocessor Architecture. Languages II. Capsules: Expressing Composable Computations in a Parallel Programming Model. Communicating Multiprocessor Tasks. An Effective Automated Approach to Specialization of Code. Flow Sensitive Loop Variant Variable Classification in Linear Time. Using ZBDDs in Points to Analysis.
Reliability. Compiler Enhanced Incremental Checkpointing. Techniques for Efficient Software Checking. Languages. Revisiting SIMD Programming. Multidimensional Blocking in UPC. An Experimental Evaluation of the New OpenMP Tasking Model. Language Extensions in Support of Compiler Parallelization. Parallel Compiler Technology I. Concurrency Analysis for Shared Memory Programs with Textually Unaligned Barriers. Iteration Disambiguation for Parallelism Identification in Time Sliced Applications. A Novel Asynchronous Software Cache Implementation for the Cell BE Processor. Pillar: A Parallel Implementation Language. Associative Parallel Containers in STAPL. Explicit Dependence Metadata in an Active Visual Effects Library. Supporting Huge Address Spaces in a Virtual Machine for Java on a Cluster. Modeling Relations between Inputs and Dynamic Behavior for General Programs. Evaluation of RDMA Opportunities in an Object Oriented DSM. Automatic Communication Performance Debugging in PGAS Languages. Parallel Compiler Technology II. Exploiting SIMD Parallelism with the CGiS Compiler Framework. Critical Block Scheduling: A Thread Level Parallelizing Mechanism for a Heterogeneous Chip Multiprocessor Architecture. Languages II. Capsules: Expressing Composable Computations in a Parallel Programming Model. Communicating Multiprocessor Tasks. An Effective Automated Approach to Specialization of Code. Flow Sensitive Loop Variant Variable Classification in Linear Time. Using ZBDDs in Points to Analysis.
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