Frederic Mallet

Logical Time @ Work for the Modeling and Analysis of Embedded Systems

Foundations of the UML/MARTE Time Model

• Broschiertes Buch

Produktbeschreibung

Logical time is a relaxed form of time promoted by synchronous languages that is functional, elastic (can be abstracted or refined), and multiform. All these properties make logical time adequate also at design time, whereas precise physical time annotations should only matter in later post-synthesis stages. The Clock Constraint Specification Language (CCSL) is a concrete language dedicated to the modeling and analysis of logical time properties. CCSL was initially defined as a companion for the time model of the UML profile for MARTE. It has now become a full-fledged domain-specific modeling language for capturing causal, chronological and timed relationships. It should complement other syntactic models to capture their underlying model of computation. This book starts by describing the historical models of concurrency that have inspired the construction of CCSL. Then, CCSL is introduced and used to build libraries dedicated to two emerging standard models from the automotive (East-ADL) and the avionic (AADL) domains. Finally, an observer-based technique to verify Esterel and VHDL implementations against CCSL specifications is presented.

Produktdetails

• Verlag: LAP Lambert Academic Publishing
• Seitenzahl: 124
• Erscheinungstermin: 19. Januar 2011
• Englisch
• Abmessung: 220mm x 150mm x 8mm
• Gewicht: 181g
• ISBN-13: 9783843393881
• ISBN-10: 3843393885
• Artikelnr.: 32761129

Autorenporträt

Dr. Eng. Habil. Frederic Mallet is een Associate Professor in de Computer Science afdeling van de Nice-Sophia Antipolis Universiteit. Hij is lid van de AOSTE onderzoekseenheid, een gezamenlijk team van het I3S laboratorium en INRIA Sophia Antipolis onderzoekscentrum. Hij is stemgerechtigd lid van de OMG revision task forces voor MARTE en SysML UML Profiles.