Low-Cost Congestion Management for NOC - Debnath, Monobrata;Lee, Junghee
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Rapid innovations in circuit integration technology have successfully integrated billions of transistors on a single chip. The advancement in IC technology has put the challenge of extracting the maximum performance gain from additional resources. In recent times, computer architects have exhorted many-core design to meet next generation computation needs. Chips, equipped with a large number of cores, bracing dynamic parallelism and modest power usage are proposed to meet future computation needs. Intriguingly, the performance of the many-core architecture greatly relies on the competence of…mehr

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Produktbeschreibung
Rapid innovations in circuit integration technology have successfully integrated billions of transistors on a single chip. The advancement in IC technology has put the challenge of extracting the maximum performance gain from additional resources. In recent times, computer architects have exhorted many-core design to meet next generation computation needs. Chips, equipped with a large number of cores, bracing dynamic parallelism and modest power usage are proposed to meet future computation needs. Intriguingly, the performance of the many-core architecture greatly relies on the competence of the on-chip interconnection network. Networks-on-Chip (NoCs) has emerged as the backbone of many-core architectures. Nevertheless, poor network performance due to congestion could become a major hindrance in the future multi-core designs. In the present research, we investigate the causes of congestion in NoCs and facilitate ways to mitigate the performance threat. In particular, the focus ofthis research is on providing cost-effective congestion management solutions suitable for NoCs.
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Autorenporträt
Monobrata Debnath a obtenu sa maîtrise en ingénierie informatique et son doctorat en ingénierie électrique en 2010 et 2016 respectivement à l'Université du Texas à San Antonio, où il travaille actuellement en tant que chercheur. Ses recherches portent sur l'architecture informatique, les réseaux sur puce, l'IdO et le multithreading simultané.