Andere Kunden interessierten sich auch für
![Low power BIST for VLSI Digital Circuits]( "Low power BIST for VLSI Digital Circuits")
Low power BIST for VLSI Digital Circuits61,99 €![Design and Implementation of Low-power]( "Design and Implementation of Low-power")
Design and Implementation of Low-power32,99 €![Low Voltage, Low Power SRAM Design]( "Low Voltage, Low Power SRAM Design")
Low Voltage, Low Power SRAM Design36,99 €![Design & Analysis of Low Power VCO for VLSI & Communication System]( "Design & Analysis of Low Power VCO for VLSI & Communication System")
Design & Analysis of Low Power VCO for VLSI & Communication System39,99 €![Low Power Operational Transconductance Amplifier]( "Low Power Operational Transconductance Amplifier")
Low Power Operational Transconductance Amplifier26,99 €![Low Power Fault Tolerant Latches and Flip-flops]( "Low Power Fault Tolerant Latches and Flip-flops")
Low Power Fault Tolerant Latches and Flip-flops44,99 €![Low Power High Performance Sequential Logic Design]( "Low Power High Performance Sequential Logic Design")
Low Power High Performance Sequential Logic Design35,99 €
The remarkable increase in transistor densities in modern VLSI systems has direct to a surge in power and energy dissipation to levels not seen before. This tendency will continue to produce as more transistors are packed into the same area. Therefore, power and energy-aware design flows are becoming trendy in both ends of the design space, high-performance and portable applications. In this study, the power and energy reduction techniques at the architecture, circuit, and device levels are presented. With the intention of diminishing power, we proposed a novel method for Conventional Array Multiplier. In the proposed design, final adder RCA is removed and the generated carry bits from the partial products are fed to the input of a full adder cell whose one of the input is zero. We applied final adder RCA removal method at the final addition stage of Column Bypassing Multiplier and Modified Booth Encoder Multiplier for low power applications. The proposed MBEM encoder is designedwith only one XOR with two inputs and two outputs. Between two outputs, one is taken at before of an inverter, the function is XNOR. The second is taken at after the inverter for XOR function.
Hinweis: Dieser Artikel kann nur an eine deutsche Lieferadresse ausgeliefert werden.
Hinweis: Dieser Artikel kann nur an eine deutsche Lieferadresse ausgeliefert werden.