Andere Kunden interessierten sich auch für
![CMOS Inverter Based Flash ADC for SoC Applications]( "CMOS Inverter Based Flash ADC for SoC Applications")
CMOS Inverter Based Flash ADC for SoC Applications26,99 €![Principles and Practices of Low Power High Speed TIQ Based Flash ADC]( "Principles and Practices of Low Power High Speed TIQ Based Flash ADC")
Principles and Practices of Low Power High Speed TIQ Based Flash ADC32,99 €![Design of Finfet Based Low Power High Speed and 3-bit Flash Adc]( "Design of Finfet Based Low Power High Speed and 3-bit Flash Adc")
Design of Finfet Based Low Power High Speed and 3-bit Flash Adc16,99 €![Designing A Flash ADC With a New Structure of 1-N Encoder]( "Designing A Flash ADC With a New Structure of 1-N Encoder")
Designing A Flash ADC With a New Structure of 1-N Encoder32,99 €![High Speed Low Offset Power Efficient Dynamic CMOS Comparator]( "High Speed Low Offset Power Efficient Dynamic CMOS Comparator")
High Speed Low Offset Power Efficient Dynamic CMOS Comparator40,99 €![Design of CMOS Low Power Folding and Interpolating ADC]( "Design of CMOS Low Power Folding and Interpolating ADC")
Design of CMOS Low Power Folding and Interpolating ADC44,99 €![A Low Power Discrete Time Band-Pass Sigma Delta Modulator ADC]( "A Low Power Discrete Time Band-Pass Sigma Delta Modulator ADC")
A Low Power Discrete Time Band-Pass Sigma Delta Modulator ADC26,99 €
In the present work, a 4-bit and a 6-bit 100 MS/s flash analog to digital converter for low power SoC application is presented. CMOS inverter has been used as a comparator for low power design. By adjusting the ratio of channel width and length, the switching threshold of the CMOS inverter is varied to detect the input analog signal. The proposed architecture has a unique feature like power supply rejection ratio (PSSR) which plays very critical role in traditional analog design. PSRR is introduced in the digital counterpart in the present design.