Murra Subba Reddy

Broschiertes Buch

Low Power Flash ADC

VLSI Technology

Beschreibung

In this project, a new design for a low power CMOS flash Analog-to-Digital Converter (ADC) is proposed. A 6-bit flash ADC, with a maximum acquisition speed of 1 GHz, is implemented in a 1.2 V analog supply voltage. Microwind simulation results for the proposed flash ADC verifying the analytical results are also given. It shows that the proposed 6-bit flash ADC consumes about 72 mW in a commercial 90 nm CMOS process. The new design offers lower number of comparators and lower power consumption compared with the traditional flash ADC.

Autor

It describes how to design a low power flash ADC which gives high speed,low cost&less complexity rather than conventional flash ADC.

Produktdetails

• Verlag: LAP Lambert Academic Publishing
• Aufl.
• Seitenzahl: 80
• Erscheinungstermin: 24. August 2011
• Englisch
• Abmessung: 220mm x 150mm x 5mm
• Gewicht: 137g
• ISBN-13: 9783845440842
• ISBN-10: 3845440848
• Artikelnr.: 35031578