Andere Kunden interessierten sich auch für
![Low Power Adiabatic Logic Design]( "Low Power Adiabatic Logic Design")
Low Power Adiabatic Logic Design32,99 €![Low Power Adiabatic Logic Using Diode Connected DC Biased PFAL]( "Low Power Adiabatic Logic Using Diode Connected DC Biased PFAL")
Low Power Adiabatic Logic Using Diode Connected DC Biased PFAL23,99 €![Comparison of Adiabatic and CMOS adders]( "Comparison of Adiabatic and CMOS adders")
Comparison of Adiabatic and CMOS adders32,99 €![Ultra Low Power Electronics and Adiabatic Solutions]( "Ultra Low Power Electronics and Adiabatic Solutions")
Ultra Low Power Electronics and Adiabatic Solutions183,99 €![Design of Low Power and High Performance Logic Circuits]( "Design of Low Power and High Performance Logic Circuits")
Design of Low Power and High Performance Logic Circuits40,99 €![High Performance Domino Logic Circuits in Low Power VLSI Design]( "High Performance Domino Logic Circuits in Low Power VLSI Design")
High Performance Domino Logic Circuits in Low Power VLSI Design32,99 €![Adiabatic Logic]( "Adiabatic Logic")
Adiabatic Logic74,99 €
The clocking schemes and signal waveforms of Adiabatic Circuits are different from those of Standard CMOS circuits. The Adiabatic Logic and Standard CMOS circuits do exist on a single chip to utilize the strength of both approaches. The interface circuits that convert signals between Adiabatic Logic and Standard CMOS circuits are inherent requirement. The text investigates design approaches of Adiabatic- CMOS and CMOS- Adiabatic interface circuits. Several new low power Adiabatic-CMOS and CMOS-Adiabatic interfaces are introduced in this text. Tanner EDA tool on BSIM3V3 90nm and 130nm CMOS technologies has been used to calculate the power consumption and power delay product of various circuits over temperature, frequencies and power supply voltages. The comparison of proposed approaches has been done with the all other approaches available in the literature on various circuit parameters. The write up concludes the efficient design approaches for interface circuits in terms of power consumption and power delay product.