Low Power Networks-on-Chip

Herausgegeben:Silvano, Cristina; Lajolo, Marcello; Palermo, Gianluca

• Broschiertes Buch

Produktbeschreibung

In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities. This book offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures.

Produktdetails

• Verlag: Springer / Springer, Berlin
• Artikelnr. des Verlages: 978-1-4899-9437-0
• 2011
• Seitenzahl: 308
• Erscheinungstermin: 20. November 2014
• Englisch
• Abmessung: 235mm x 155mm x 17mm
• Gewicht: 474g
• ISBN-13: 9781489994370
• ISBN-10: 1489994378
• Artikelnr.: 41903489

Inhaltsangabe

Network-on-Chip Power Estimation.- Timing.- synchronous/asynchronous communication.- Network-on-Chip link design.- Topology exploration.- Network-on-Chip support for CMP/MPSoCs.- Network design for 3D stacked logic and memory.- Beyond the wired Network-on-Chip.

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Network-on-Chip Power Estimation.- Timing.- synchronous/asynchronous communication.- Network-on-Chip link design.- Topology exploration.- Network-on-Chip support for CMP/MPSoCs.- Network design for 3D stacked logic and memory.- Beyond the wired Network-on-Chip.