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Aim of this work is to outline a new methodological
flow that allows system designers to make use of
Dynamic Reconfiguration in a new and intuitive way.
As a matter of fact, Dynamic Reconfiguration can lead
to enormous improvements in embedded systems design,
but it is, at the same time, characterized by
complexity and toughness of use. The proposed
methodological flow is centered on the model-based
design paradigm; it relies upon Simulink by The
MathWorks as long as several tools developed by the
DRESD team (www.dresd.org) and by the targeted FPGAs
producers. The main issue addressed is the
implementation of large designs onto FPGAs with
limited available resources. By applying the normal
synthesis process to these systems the outcome will
be a failure due to the lack of resources. A flow
based on Dynamic Partial Reconfigurability will
instead allow its successful implementation: since
systems are composed of blocks which need
intermediate input(s) and produce intermediate
output(s), these blocks can be separately synthesized
a priori and then hard-coded onto the PLD when their
functionalities become necessary.
flow that allows system designers to make use of
Dynamic Reconfiguration in a new and intuitive way.
As a matter of fact, Dynamic Reconfiguration can lead
to enormous improvements in embedded systems design,
but it is, at the same time, characterized by
complexity and toughness of use. The proposed
methodological flow is centered on the model-based
design paradigm; it relies upon Simulink by The
MathWorks as long as several tools developed by the
DRESD team (www.dresd.org) and by the targeted FPGAs
producers. The main issue addressed is the
implementation of large designs onto FPGAs with
limited available resources. By applying the normal
synthesis process to these systems the outcome will
be a failure due to the lack of resources. A flow
based on Dynamic Partial Reconfigurability will
instead allow its successful implementation: since
systems are composed of blocks which need
intermediate input(s) and produce intermediate
output(s), these blocks can be separately synthesized
a priori and then hard-coded onto the PLD when their
functionalities become necessary.