David A. Papa, Igor L. Markov

Multi-Objective Optimization in Physical Synthesis of Integrated Circuits

• Gebundenes Buch

Produktbeschreibung

This book introduces techniques that advance the capabilities and strength of modern software tools for physical synthesis, with the ultimate goal to improve the quality of leading-edge semiconductor products. It provides a comprehensive introduction to physical synthesis and takes the reader methodically from first principles through state-of-the-art optimizations used in cutting edge industrial tools. It explains how to integrate chip optimizations in novel ways to create powerful circuit transformations that help satisfy performance requirements.

Produktdetails

• Lecture Notes in Electrical Engineering 166
• Verlag: Springer / Springer New York / Springer, Berlin
• Artikelnr. des Verlages: 80074169, 978-1-4614-1355-4
• 2012
• Seitenzahl: 168
• Erscheinungstermin: 8. August 2012
• Englisch
• Abmessung: 241mm x 160mm x 13mm
• Gewicht: 368g
• ISBN-13: 9781461413554
• ISBN-10: 1461413559
• Artikelnr.: 33708027

Inhaltsangabe

Part I: Introduction and Prior Art.- Timing Closure for Multi-Million-Gate Integrated Circuits.- State of the Art in Physical Synthesis.- Part II: Local Physical Synthesis and Necessary Analysis Techniques.- Buffer Insertion during Timing-Driven Placement.- Bounded Transactional Timing Analysis.- Gate Sizing During Timing-Driven Placement.- Part III: Broadening the Scope of Circuit Transformations.- Physically-Driven Logic Restructuring.- Logic Restructuring as an Aid to Physical Retiming.- Broadening the Scope of Optimization using Partitioning.- Co-Optimization of Latches and Clock Networks.- Conclusions and Future Work.

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Part I: Introduction and Prior Art.- Timing Closure for Multi-Million-Gate Integrated Circuits.- State of the Art in Physical Synthesis.- Part II: Local Physical Synthesis and Necessary Analysis Techniques.- Buffer Insertion during Timing-Driven Placement.- Bounded Transactional Timing Analysis.- Gate Sizing During Timing-Driven Placement.- Part III: Broadening the Scope of Circuit Transformations.- Physically-Driven Logic Restructuring.- Logic Restructuring as an Aid to Physical Retiming.- Broadening the Scope of Optimization using Partitioning.- Co-Optimization of Latches and Clock Networks.- Conclusions and Future Work.