Ban Wong, Anurag Mittal, Yu Cao, Greg W Starr
Nano-CMOS Circuit and Physical Design
By Ban Wong, Anurag Mittal, Yu Cao et al.
Ban Wong, Anurag Mittal, Yu Cao, Greg W Starr
Nano-CMOS Circuit and Physical Design
By Ban Wong, Anurag Mittal, Yu Cao et al.
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Based on the authors' expansive collection of notes taken over the years, Nano-CMOS Circuit and Physical Design bridges the gap between physical and circuit design and fabrication processing, manufacturability, and yield. This innovative book covers: process technology, including sub-wavelength optical lithography; impact of process scaling on circuit and physical implementation and low power with leaky transistors; and DFM, yield, and the impact of physical implementation.
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Based on the authors' expansive collection of notes taken over the years, Nano-CMOS Circuit and Physical Design bridges the gap between physical and circuit design and fabrication processing, manufacturability, and yield. This innovative book covers: process technology, including sub-wavelength optical lithography; impact of process scaling on circuit and physical implementation and low power with leaky transistors; and DFM, yield, and the impact of physical implementation.
Produktdetails
- Produktdetails
- Verlag: Wiley & Sons
- Artikelnr. des Verlages: 14646610000
- 1. Auflage
- Seitenzahl: 393
- Erscheinungstermin: 1. Dezember 2004
- Deutsch, Englisch
- Abmessung: 240mm x 161mm x 27mm
- Gewicht: 708g
- ISBN-13: 9780471466109
- ISBN-10: 0471466107
- Artikelnr.: 13067594
- Verlag: Wiley & Sons
- Artikelnr. des Verlages: 14646610000
- 1. Auflage
- Seitenzahl: 393
- Erscheinungstermin: 1. Dezember 2004
- Deutsch, Englisch
- Abmessung: 240mm x 161mm x 27mm
- Gewicht: 708g
- ISBN-13: 9780471466109
- ISBN-10: 0471466107
- Artikelnr.: 13067594
Tao Wong is a Canadian author based in Toronto who is best known for his System Apocalypse post-apocalyptic LitRPG series and A Thousand Li, a Chinese xianxia fantasy series. His work has been released in audio, paperback, hardcover and ebook formats and translated into German, Spanish, Portuguese, Russian and other languages. He was shortlisted for the UK Kindle Storyteller award in 2021 for his work, A Thousand Li: the Second Sect.When he's not writing and working, he's practicing martial arts, reading and dreaming up new worlds.Tao became a full-time author in 2019 and is a member of SF Canada, the Science Fiction and Fantasy Writers of America (SFWA) and ALLI.
1. Nano-CMOS scaling issues and implications. 1.1. Design methodology in
the nano-CMOS era - an introduction. 1.2. Physical Scaling Near Limit -
innovations needed to continue performance scaling. 1.3. An overview of
Sub-100nm scaling challenges and sub-wavelength Optical Lithography. 1.4.
Process issues. 1.5. Lithography issues and mask data explosion. 1.6. New
breed of Circuit and Physical Design Engineers. 1.7. Modeling challenges.
1.8. The need for Design Methodology changes for performance as well as to
mitigate Mask Cost, Scalability and Manufacturability - an overview 1.9.
Summary. PART 1. PROCESS TECHNOLOGY AND SUB-WAVELENGTH OPTICAL LITHOGRAPHY
PHYSICS, THEORY OF OPERATION, ISSUES AND SOLUTIONS. 2. CMOS Device and
Process Technology. 2.1 Equipment Requirements For Front-End Processing.
2.2 Front-End Device Issues of the CMOS Scaling. 2.3 Back-End-of-Line
(BEOL) Technology. 3. Theory and Practicalities of Sub-Wavelength Optical
Lithography. 3.1 Introduction and simple imaging theory. 3.2 Challenges for
the 100 nm Node. 3.3 Resolution Enhancement Techniques: Physics. 3.4
Physical Design Style Impact on RET and OPC Complexity. 3.5 The Road Ahead:
Future Lithography Technologies. PART 2. PROCESS SCALING IMPACT ON DESIGN.
4 Mixed Signal Circuit Design. 4.1 Introduction. 4.2 Issue Overview. 4.3
Device Modeling. 4.4 Passive Components. 4.5 Design Methododolgy. 4.6 Low
Voltage Techniques. 4.7 Design Procedures. 4.8 ESD Protection. 4.9 Noise
Isolation. 4.10 Decoupling. 4.11 Power Busing. 4.12 Integration Issues.
4.13 Summary. 5. ESD Protection Design. 5.1 Introduction. 5.2 ESD Standards
and Models. 5.3 Basic Concept of ESD Protection Design. 5.4 Low-C ESD
Protection Design for High-Speed I/O. 5.5 ESD Protection Design for
Mixed-Voltage I/O. 5.6 SCR Devices for ESD Protection. 5.7 Summary. 6. IO
Design. 6.1 IO Standards. 6.2 Signal Transfer. 6.3 ESD Protection. 6.4 I/O
Switching Noise. 6.5 Termination. 6.6 Impedance Matching. 6.7 Pre-Emphasis.
6.8 Equalization. 6.9 Conclusions. 7. DRAM. 7.1 Introduction. 7.2 DRAM
basics. 7.3 Scaling of the capacitor. 7.4 Scaling of the array-transistor.
7.5 Scaling of the sense-amplifier. 7.6 Summary. 8. Chapter 8 Signal
Integrity Issues in On-Chip Interconnect. 8.1. Introduction. 8.2.
Interconnect Parasitics Extraction. 8.3. Signal Integrity Analysis. 8.4.
Design Solutions for Signal Integrity. 8.5. Summary. 9 Ultra Low Power
Circuit Design. 9.1 Introduction on ultra low power design. 9.2 Design-time
low power techniques. 9.3 Run-time low power techniques. 9.4 Technology
innovations for low power design. 9.5 Perspectives for future ultra low
power design. 10 Reference. PART 3. IMPACT OF PHYSICAL DESIGN ON
MANUFACTURING/YIELD AND PERFORMANCE. 10 Design For Manufacturability (DFM).
10.1 Motivation. 10.2 Comparison of optimal and sub-optimal layouts. 10.3
Global Route DFM. 10.4 Analog DFM. 10.5 Some Rules of Thumb. 10.6 Summary.
11. Design for Variability. 11.1. Impact of Variations on Future Design.
11.2. Strategies to Mitigate Impact due to Variations. 11.3. Corner
Modeling Methodology for nano-CMOS Processes. 11.4. New Features of the
BSIM4 Model. 11.5. Summary.
the nano-CMOS era - an introduction. 1.2. Physical Scaling Near Limit -
innovations needed to continue performance scaling. 1.3. An overview of
Sub-100nm scaling challenges and sub-wavelength Optical Lithography. 1.4.
Process issues. 1.5. Lithography issues and mask data explosion. 1.6. New
breed of Circuit and Physical Design Engineers. 1.7. Modeling challenges.
1.8. The need for Design Methodology changes for performance as well as to
mitigate Mask Cost, Scalability and Manufacturability - an overview 1.9.
Summary. PART 1. PROCESS TECHNOLOGY AND SUB-WAVELENGTH OPTICAL LITHOGRAPHY
PHYSICS, THEORY OF OPERATION, ISSUES AND SOLUTIONS. 2. CMOS Device and
Process Technology. 2.1 Equipment Requirements For Front-End Processing.
2.2 Front-End Device Issues of the CMOS Scaling. 2.3 Back-End-of-Line
(BEOL) Technology. 3. Theory and Practicalities of Sub-Wavelength Optical
Lithography. 3.1 Introduction and simple imaging theory. 3.2 Challenges for
the 100 nm Node. 3.3 Resolution Enhancement Techniques: Physics. 3.4
Physical Design Style Impact on RET and OPC Complexity. 3.5 The Road Ahead:
Future Lithography Technologies. PART 2. PROCESS SCALING IMPACT ON DESIGN.
4 Mixed Signal Circuit Design. 4.1 Introduction. 4.2 Issue Overview. 4.3
Device Modeling. 4.4 Passive Components. 4.5 Design Methododolgy. 4.6 Low
Voltage Techniques. 4.7 Design Procedures. 4.8 ESD Protection. 4.9 Noise
Isolation. 4.10 Decoupling. 4.11 Power Busing. 4.12 Integration Issues.
4.13 Summary. 5. ESD Protection Design. 5.1 Introduction. 5.2 ESD Standards
and Models. 5.3 Basic Concept of ESD Protection Design. 5.4 Low-C ESD
Protection Design for High-Speed I/O. 5.5 ESD Protection Design for
Mixed-Voltage I/O. 5.6 SCR Devices for ESD Protection. 5.7 Summary. 6. IO
Design. 6.1 IO Standards. 6.2 Signal Transfer. 6.3 ESD Protection. 6.4 I/O
Switching Noise. 6.5 Termination. 6.6 Impedance Matching. 6.7 Pre-Emphasis.
6.8 Equalization. 6.9 Conclusions. 7. DRAM. 7.1 Introduction. 7.2 DRAM
basics. 7.3 Scaling of the capacitor. 7.4 Scaling of the array-transistor.
7.5 Scaling of the sense-amplifier. 7.6 Summary. 8. Chapter 8 Signal
Integrity Issues in On-Chip Interconnect. 8.1. Introduction. 8.2.
Interconnect Parasitics Extraction. 8.3. Signal Integrity Analysis. 8.4.
Design Solutions for Signal Integrity. 8.5. Summary. 9 Ultra Low Power
Circuit Design. 9.1 Introduction on ultra low power design. 9.2 Design-time
low power techniques. 9.3 Run-time low power techniques. 9.4 Technology
innovations for low power design. 9.5 Perspectives for future ultra low
power design. 10 Reference. PART 3. IMPACT OF PHYSICAL DESIGN ON
MANUFACTURING/YIELD AND PERFORMANCE. 10 Design For Manufacturability (DFM).
10.1 Motivation. 10.2 Comparison of optimal and sub-optimal layouts. 10.3
Global Route DFM. 10.4 Analog DFM. 10.5 Some Rules of Thumb. 10.6 Summary.
11. Design for Variability. 11.1. Impact of Variations on Future Design.
11.2. Strategies to Mitigate Impact due to Variations. 11.3. Corner
Modeling Methodology for nano-CMOS Processes. 11.4. New Features of the
BSIM4 Model. 11.5. Summary.
1. Nano-CMOS scaling issues and implications. 1.1. Design methodology in
the nano-CMOS era - an introduction. 1.2. Physical Scaling Near Limit -
innovations needed to continue performance scaling. 1.3. An overview of
Sub-100nm scaling challenges and sub-wavelength Optical Lithography. 1.4.
Process issues. 1.5. Lithography issues and mask data explosion. 1.6. New
breed of Circuit and Physical Design Engineers. 1.7. Modeling challenges.
1.8. The need for Design Methodology changes for performance as well as to
mitigate Mask Cost, Scalability and Manufacturability - an overview 1.9.
Summary. PART 1. PROCESS TECHNOLOGY AND SUB-WAVELENGTH OPTICAL LITHOGRAPHY
PHYSICS, THEORY OF OPERATION, ISSUES AND SOLUTIONS. 2. CMOS Device and
Process Technology. 2.1 Equipment Requirements For Front-End Processing.
2.2 Front-End Device Issues of the CMOS Scaling. 2.3 Back-End-of-Line
(BEOL) Technology. 3. Theory and Practicalities of Sub-Wavelength Optical
Lithography. 3.1 Introduction and simple imaging theory. 3.2 Challenges for
the 100 nm Node. 3.3 Resolution Enhancement Techniques: Physics. 3.4
Physical Design Style Impact on RET and OPC Complexity. 3.5 The Road Ahead:
Future Lithography Technologies. PART 2. PROCESS SCALING IMPACT ON DESIGN.
4 Mixed Signal Circuit Design. 4.1 Introduction. 4.2 Issue Overview. 4.3
Device Modeling. 4.4 Passive Components. 4.5 Design Methododolgy. 4.6 Low
Voltage Techniques. 4.7 Design Procedures. 4.8 ESD Protection. 4.9 Noise
Isolation. 4.10 Decoupling. 4.11 Power Busing. 4.12 Integration Issues.
4.13 Summary. 5. ESD Protection Design. 5.1 Introduction. 5.2 ESD Standards
and Models. 5.3 Basic Concept of ESD Protection Design. 5.4 Low-C ESD
Protection Design for High-Speed I/O. 5.5 ESD Protection Design for
Mixed-Voltage I/O. 5.6 SCR Devices for ESD Protection. 5.7 Summary. 6. IO
Design. 6.1 IO Standards. 6.2 Signal Transfer. 6.3 ESD Protection. 6.4 I/O
Switching Noise. 6.5 Termination. 6.6 Impedance Matching. 6.7 Pre-Emphasis.
6.8 Equalization. 6.9 Conclusions. 7. DRAM. 7.1 Introduction. 7.2 DRAM
basics. 7.3 Scaling of the capacitor. 7.4 Scaling of the array-transistor.
7.5 Scaling of the sense-amplifier. 7.6 Summary. 8. Chapter 8 Signal
Integrity Issues in On-Chip Interconnect. 8.1. Introduction. 8.2.
Interconnect Parasitics Extraction. 8.3. Signal Integrity Analysis. 8.4.
Design Solutions for Signal Integrity. 8.5. Summary. 9 Ultra Low Power
Circuit Design. 9.1 Introduction on ultra low power design. 9.2 Design-time
low power techniques. 9.3 Run-time low power techniques. 9.4 Technology
innovations for low power design. 9.5 Perspectives for future ultra low
power design. 10 Reference. PART 3. IMPACT OF PHYSICAL DESIGN ON
MANUFACTURING/YIELD AND PERFORMANCE. 10 Design For Manufacturability (DFM).
10.1 Motivation. 10.2 Comparison of optimal and sub-optimal layouts. 10.3
Global Route DFM. 10.4 Analog DFM. 10.5 Some Rules of Thumb. 10.6 Summary.
11. Design for Variability. 11.1. Impact of Variations on Future Design.
11.2. Strategies to Mitigate Impact due to Variations. 11.3. Corner
Modeling Methodology for nano-CMOS Processes. 11.4. New Features of the
BSIM4 Model. 11.5. Summary.
the nano-CMOS era - an introduction. 1.2. Physical Scaling Near Limit -
innovations needed to continue performance scaling. 1.3. An overview of
Sub-100nm scaling challenges and sub-wavelength Optical Lithography. 1.4.
Process issues. 1.5. Lithography issues and mask data explosion. 1.6. New
breed of Circuit and Physical Design Engineers. 1.7. Modeling challenges.
1.8. The need for Design Methodology changes for performance as well as to
mitigate Mask Cost, Scalability and Manufacturability - an overview 1.9.
Summary. PART 1. PROCESS TECHNOLOGY AND SUB-WAVELENGTH OPTICAL LITHOGRAPHY
PHYSICS, THEORY OF OPERATION, ISSUES AND SOLUTIONS. 2. CMOS Device and
Process Technology. 2.1 Equipment Requirements For Front-End Processing.
2.2 Front-End Device Issues of the CMOS Scaling. 2.3 Back-End-of-Line
(BEOL) Technology. 3. Theory and Practicalities of Sub-Wavelength Optical
Lithography. 3.1 Introduction and simple imaging theory. 3.2 Challenges for
the 100 nm Node. 3.3 Resolution Enhancement Techniques: Physics. 3.4
Physical Design Style Impact on RET and OPC Complexity. 3.5 The Road Ahead:
Future Lithography Technologies. PART 2. PROCESS SCALING IMPACT ON DESIGN.
4 Mixed Signal Circuit Design. 4.1 Introduction. 4.2 Issue Overview. 4.3
Device Modeling. 4.4 Passive Components. 4.5 Design Methododolgy. 4.6 Low
Voltage Techniques. 4.7 Design Procedures. 4.8 ESD Protection. 4.9 Noise
Isolation. 4.10 Decoupling. 4.11 Power Busing. 4.12 Integration Issues.
4.13 Summary. 5. ESD Protection Design. 5.1 Introduction. 5.2 ESD Standards
and Models. 5.3 Basic Concept of ESD Protection Design. 5.4 Low-C ESD
Protection Design for High-Speed I/O. 5.5 ESD Protection Design for
Mixed-Voltage I/O. 5.6 SCR Devices for ESD Protection. 5.7 Summary. 6. IO
Design. 6.1 IO Standards. 6.2 Signal Transfer. 6.3 ESD Protection. 6.4 I/O
Switching Noise. 6.5 Termination. 6.6 Impedance Matching. 6.7 Pre-Emphasis.
6.8 Equalization. 6.9 Conclusions. 7. DRAM. 7.1 Introduction. 7.2 DRAM
basics. 7.3 Scaling of the capacitor. 7.4 Scaling of the array-transistor.
7.5 Scaling of the sense-amplifier. 7.6 Summary. 8. Chapter 8 Signal
Integrity Issues in On-Chip Interconnect. 8.1. Introduction. 8.2.
Interconnect Parasitics Extraction. 8.3. Signal Integrity Analysis. 8.4.
Design Solutions for Signal Integrity. 8.5. Summary. 9 Ultra Low Power
Circuit Design. 9.1 Introduction on ultra low power design. 9.2 Design-time
low power techniques. 9.3 Run-time low power techniques. 9.4 Technology
innovations for low power design. 9.5 Perspectives for future ultra low
power design. 10 Reference. PART 3. IMPACT OF PHYSICAL DESIGN ON
MANUFACTURING/YIELD AND PERFORMANCE. 10 Design For Manufacturability (DFM).
10.1 Motivation. 10.2 Comparison of optimal and sub-optimal layouts. 10.3
Global Route DFM. 10.4 Analog DFM. 10.5 Some Rules of Thumb. 10.6 Summary.
11. Design for Variability. 11.1. Impact of Variations on Future Design.
11.2. Strategies to Mitigate Impact due to Variations. 11.3. Corner
Modeling Methodology for nano-CMOS Processes. 11.4. New Features of the
BSIM4 Model. 11.5. Summary.