Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, Chita R. Das

Network-On-Chip Architectures

A Holistic Design Exploration

• Gebundenes Buch

Produktbeschreibung

NoC architectures are seen as a possible solution to burgeoning global wiring delays in many-core chips, and this work deals with the main issues that need to be resolved in performance, energy efficiency, reliability, variability and silicon area consumption.

---

[2]. The Cell Processor from Sony, Toshiba and IBM (STI) [3], and the Sun UltraSPARC T1 (formerly codenamed Niagara) [4] signal the growing popularity of such systems. Furthermore, Intel's very recently announced 80-core TeraFLOP chip [5] exemplifies the irreversible march toward many-core systems with tens or even hundreds of processing elements. 1.2 The Dawn of the Communication-Centric Revolution The multi-core thrust has ushered the gradual displacement of the computati- centric design model by a more communication-centric approach [6]. The large, sophisticated monolithic modules are giving way to several smaller, simpler p- cessing elements working in tandem. This trend has led to a surge in the popularity of multi-core systems, which typically manifest themselves in two distinct incarnations: heterogeneous Multi-Processor Systems-on-Chip (MPSoC) and homogeneous Chip Multi-Processors (CMP). The SoC philosophy revolves around the technique of Platform-Based Design (PBD) [7], which advocates the reuse of Intellectual Property (IP) cores in flexible design templates that can be customized accordingly to satisfy the demands of particular implementations. The appeal of such a modular approach lies in the substantially reduced Time-To- Market (TTM) incubation period, which is a direct outcome of lower circuit complexity and reduced design effort. The whole system can now be viewed as a diverse collection of pre-existing IP components integrated on a single die.

Produktdetails

• Lecture Notes in Electrical Engineering 45
• Verlag: Springer / Springer Netherlands
• Artikelnr. des Verlages: 12631650, 978-90-481-3030-6
• 2010 edition
• Seitenzahl: 223
• Erscheinungstermin: 7. Oktober 2009
• Englisch
• Abmessung: 242mm x 166mm x 23mm
• Gewicht: 528g
• ISBN-13: 9789048130306
• ISBN-10: 9048130301
• Artikelnr.: 26574734

Inhaltsangabe

MICRO-Architectural Exploration.- A Baseline NoC Architecture.- ViChaR: A Dynamic Virtual Channel Regulator for NoC Routers [39].- RoCo: The Row-Column Decoupled Router - A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks [40].- Exploring FaultoTolerant Network-on-Chip Architectures [37].- On the Effects of Process Variation in Network-on-Chip Architectures [45].- MACRO-Architectural Exploration.- The Quest for Scalable On-Chip Interconnection Networks: Bus/NoC Hybridization [15].- Design and Management of 3D Chip Multiprocessors Using Network-In-Memory (NetInMem) [43].- A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures [44].- Digest of Additional NoC MACRO-Architectural Research.- Conclusions and Future Work.