Andere Kunden interessierten sich auch für
![MEMORY HIERARCHY DESIGN FOR CHIP MULTIPROCESSORS]( "MEMORY HIERARCHY DESIGN FOR CHIP MULTIPROCESSORS")
MEMORY HIERARCHY DESIGN FOR CHIP MULTIPROCESSORS38,99 €![Test Planning for Core-based Systems-on-chip]( "Test Planning for Core-based Systems-on-chip")
Test Planning for Core-based Systems-on-chip38,99 €![Source-Synchronous Networks-On-Chip]( "Source-Synchronous Networks-On-Chip")
Source-Synchronous Networks-On-Chip74,99 €![Source-Synchronous Networks-On-Chip]( "Source-Synchronous Networks-On-Chip")
Source-Synchronous Networks-On-Chip74,99 €![Reliability, Availability and Serviceability of Networks-on-Chip]( "Reliability, Availability and Serviceability of Networks-on-Chip")
Reliability, Availability and Serviceability of Networks-on-Chip76,99 €![VLSI-SoC: The Advanced Research for Systems on Chip]( "VLSI-SoC: The Advanced Research for Systems on Chip")
VLSI-SoC: The Advanced Research for Systems on Chip37,99 €![Low Power Networks-on-Chip]( "Low Power Networks-on-Chip")
Low Power Networks-on-Chip74,99 €
Network-on-Chip (NoC) is communication infrastructure
for future multi-core Systems-on-Chip (SoCs). NoCs
are expected to overcome scalability and performance
limitations of Point-to-Point (P2P) and bus-based
communication systems. The routing algorithm of a
given NoC affects the performance of the system
measured with respect to metrics such as latency,
throughput and load distribution. In this work, the
popular Orthogonal One Turn (O1TURN) and Dimension
Order Routing algorithms (DOR) for 2D-meshes are
implemented by computer simulation. Investigation of
the effect of parameters such as packet, buffer, and
topology sizes on the performance of the network
showed that the center of the network is loaded more
than the edges. A DOR algorithm with modified flit
injection policy is evaluated to achieve a more
balanced load distribution. This book explains basic
concepts of On-Chip Networks and can be used as an
introductory material.
for future multi-core Systems-on-Chip (SoCs). NoCs
are expected to overcome scalability and performance
limitations of Point-to-Point (P2P) and bus-based
communication systems. The routing algorithm of a
given NoC affects the performance of the system
measured with respect to metrics such as latency,
throughput and load distribution. In this work, the
popular Orthogonal One Turn (O1TURN) and Dimension
Order Routing algorithms (DOR) for 2D-meshes are
implemented by computer simulation. Investigation of
the effect of parameters such as packet, buffer, and
topology sizes on the performance of the network
showed that the center of the network is loaded more
than the edges. A DOR algorithm with modified flit
injection policy is evaluated to achieve a more
balanced load distribution. This book explains basic
concepts of On-Chip Networks and can be used as an
introductory material.