Andere Kunden interessierten sich auch für
![Noise-Shaping All-Digital Phase-Locked Loops]( "Noise-Shaping All-Digital Phase-Locked Loops")
Noise-Shaping All-Digital Phase-Locked Loops74,99 €![Low-Noise Low-Power Design for Phase-Locked Loops]( "Low-Noise Low-Power Design for Phase-Locked Loops")
Low-Noise Low-Power Design for Phase-Locked Loops74,99 €![Low-Noise Low-Power Design for Phase-Locked Loops]( "Low-Noise Low-Power Design for Phase-Locked Loops")
Low-Noise Low-Power Design for Phase-Locked Loops74,99 €![60-GHz CMOS Phase-Locked Loops]( "60-GHz CMOS Phase-Locked Loops")
60-GHz CMOS Phase-Locked Loops74,99 €![Minimizing Spurious Tones in Digital Delta-Sigma Modulators]( "Minimizing Spurious Tones in Digital Delta-Sigma Modulators")
Minimizing Spurious Tones in Digital Delta-Sigma Modulators66,99 €![Design of CMOS Phase-Locked Loops]( "Design of CMOS Phase-Locked Loops")
Design of CMOS Phase-Locked Loops102,99 €![CMOS 60-GHz and E-band Power Amplifiers and Transmitters]( "CMOS 60-GHz and E-band Power Amplifiers and Transmitters")
CMOS 60-GHz and E-band Power Amplifiers and Transmitters74,99 €
This book presents a novel approach to the analysis and design of all-digital phase-locked loops (ADPLLs), technology widely used in wireless communication devices. The authors provide an overview of ADPLL architectures, time-to-digital converters (TDCs) and noise shaping. Realistic examples illustrate how to analyze and simulate phase noise in the presence of sigma-delta modulation and time-to-digital conversion. Readers will gain a deep understanding of ADPLLs and the central role played by noise-shaping. A range of ADPLL and TDC architectures are presented in unified manner. Analytical and simulation tools are discussed in detail. Matlab code is included that can be reused to design, simulate and analyze the ADPLL architectures that are presented in the book.