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The work presents two high-speed, low-power full adder cells designed with alternative internal logic structures, Gate Diffusion Input (GDI) logic styles, and hybrid CMOS logic styles to reduce Power Delay Product (PDP). This adder module was designed to be low-power, high-speed, and full-voltage swing. First design uses hybrid logic. The second design eliminates the need for XOR/XNOR gates for designing full adder cells and uses GDI (Gate-Diffusion-Input) to provide a low-power, high-speed digital component with full voltage swing. The work compares speed and power consumption of other low-PDP full adders. All full adders were designed with 180nm technology and tested using a comprehensive test bench that measured in-out current and power supply current. Simulations should show that the proposed full adder has an 80 percent PDP advantage over its counterpart.