Phase-Locked Frequency Generation and Clocking

Architectures and Circuits for Modern Wireless and Wireline Systems
Herausgeber: Rhee, Woogeun

• Gebundenes Buch

Produktbeschreibung

This book covers essential topics and issues in current Phase-Locked Loop design, from fundamentals to practical design aspects. Both wireless and wireline systems are considered in the design of low noise frequency generation and clocking systems.

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Produktdetails

• Verlag: Institution of Engineering & Technology
• Seitenzahl: 736
• Erscheinungstermin: 9. Juni 2020
• Englisch
• Abmessung: 241mm x 163mm x 38mm
• Gewicht: 1270g
• ISBN-13: 9781785618857
• ISBN-10: 1785618857
• Artikelnr.: 58033829

Inhaltsangabe

1. Part I: Basic architectures and system perspectives
* Chapter 1: Evolution of monolithic phase-locked loops
* Chapter 2: Fractional-N frequency synthesis
* Chapter 3: Clock data recovery: a system perspective
* Chapter 4: Silicon-based THz frequency synthesizers with wide locking
range
2. Part II: Digital-intensive phase-locked loops
* Chapter 5: Time-to-digital converters
* Chapter 6: Bang-bang digital PLLs for wireless systems
* Chapter 7: Hybrid PLLs
* Chapter 8: Spur mitigation techniques for DPLL architecture
* Chapter 9: Fully synthesized digital PLL
* Chapter 10: Ultra-low-power ADPLL
3. Part III: Low-noise frequency generation and modulation
* Chapter 11: Integrated LC oscillators
* Chapter 12: Mm-wave and sub-THz CMOS VCOs
* Chapter 13: Ultra-low phase noise ADPLL for millimeter wave
* Chapter 14: DTC-based subsampling PLLs for low-noise synthesis and
two-point modulation
* Chapter 15: Hybrid two-point modulation with 1b high-pass modulation
and embedded FIR filtering
4. Part IV: Clock-and-data recovery and clocking
* Chapter 16: An overview of CDR in ultra-high-speed wireline
transceivers
* Chapter 17: Clock and data recovery for optical links
* Chapter 18: Digital clock and data recovery circuits
* Chapter 19: Spread spectrum clock generator: a low-cost EMI solution
* Chapter 20: High-performance CMOS clock distribution
5. Part V: Advanced clock/frequency generation
* Chapter 21: Sub-sampling PLL techniques
* Chapter 22: PLLs with nested frequency-locked loop
* Chapter 23: Time amplified charge pump PLL
* Chapter 24: Multiplying DLLs
* Chapter 25: Wideband PLLs