This volume introduces innovative power estimation and optimization methodologies to support the design of low power embedded systems based on high-performance VLIW microprocessors. A VLIW processor is a (generally) pipelined processor that can execute, in each clock cycle, a set of explicitly parallel operations.
This volume introduces innovative power estimation and optimization methodologies to support the design of low power embedded systems based on high-performance VLIW microprocessors. A VLIW processor is a (generally) pipelined processor that can execute, in each clock cycle, a set of explicitly parallel operations. Hinweis: Dieser Artikel kann nur an eine deutsche Lieferadresse ausgeliefert werden.
Power Estimation Methods.- Background.- Instruction-Level Power Estimation for VLIW Processor Cores.- Software Power Estimation of the LX Core: A Case Study.- System-Level Power Estimation for the LX Architecture.- Microprocessor Abstraction Levels.- Power Optimization Methods.- Background.- A Micro-Architectural Optimization for Low Power.- A Design Space Exploration Methodology.- Conclusions and future work.
Power Estimation Methods.- Background.- Instruction-Level Power Estimation for VLIW Processor Cores.- Software Power Estimation of the LX Core: A Case Study.- System-Level Power Estimation for the LX Architecture.- Microprocessor Abstraction Levels.- Power Optimization Methods.- Background.- A Micro-Architectural Optimization for Low Power.- A Design Space Exploration Methodology.- Conclusions and future work.
Power Estimation Methods.- Background.- Instruction-Level Power Estimation for VLIW Processor Cores.- Software Power Estimation of the LX Core: A Case Study.- System-Level Power Estimation for the LX Architecture.- Microprocessor Abstraction Levels.- Power Optimization Methods.- Background.- A Micro-Architectural Optimization for Low Power.- A Design Space Exploration Methodology.- Conclusions and future work.
Power Estimation Methods.- Background.- Instruction-Level Power Estimation for VLIW Processor Cores.- Software Power Estimation of the LX Core: A Case Study.- System-Level Power Estimation for the LX Architecture.- Microprocessor Abstraction Levels.- Power Optimization Methods.- Background.- A Micro-Architectural Optimization for Low Power.- A Design Space Exploration Methodology.- Conclusions and future work.
Es gelten unsere Allgemeinen Geschäftsbedingungen: www.buecher.de/agb
Impressum
www.buecher.de ist ein Internetauftritt der buecher.de internetstores GmbH
Geschäftsführung: Monica Sawhney | Roland Kölbl | Günter Hilger
Sitz der Gesellschaft: Batheyer Straße 115 - 117, 58099 Hagen
Postanschrift: Bürgermeister-Wegele-Str. 12, 86167 Augsburg
Amtsgericht Hagen HRB 13257
Steuernummer: 321/5800/1497