Andere Kunden interessierten sich auch für
![Analog Design Essentials]( "Analog Design Essentials")
Analog Design Essentials64,99 €![Analog Design Issues in Digital VLSI Circuits and Systems]( "Analog Design Issues in Digital VLSI Circuits and Systems")
Analog Design Issues in Digital VLSI Circuits and Systems74,99 €![Regular Fabrics in Deep Sub-Micron Integrated-Circuit Design]( "Regular Fabrics in Deep Sub-Micron Integrated-Circuit Design")
Regular Fabrics in Deep Sub-Micron Integrated-Circuit Design74,99 €![Low-Power Design Techniques and CAD Tools for Analog and RF Integrated Circuits]( "Low-Power Design Techniques and CAD Tools for Analog and RF Integrated Circuits")
Low-Power Design Techniques and CAD Tools for Analog and RF Integrated Circuits110,99 €![Crucial Issues in Semiconductor Materials and Processing Technologies]( "Crucial Issues in Semiconductor Materials and Processing Technologies")
Crucial Issues in Semiconductor Materials and Processing Technologies166,99 €![High Frequency Continuous Time Filters in Digital CMOS Processes]( "High Frequency Continuous Time Filters in Digital CMOS Processes")
High Frequency Continuous Time Filters in Digital CMOS Processes74,99 €![IDDQ Testing of VLSI Circuits]( "IDDQ Testing of VLSI Circuits")
IDDQ Testing of VLSI Circuits83,99 €
In the deep sub-micron regime, the power consumption has become one of the most important issues for competitive design of digital circuits. Due to dramatically increasing leakage currents, the power consumption does not take advantage of technology scaling as before. State-of-art power reduction techniques like the use of multiple supply and threshold voltages, transistor stack forcing and power gating are discussed with respect to implementation and power saving capability. Focus is given especially on technology dependencies, process variations and technology scaling. Design and implementation issues are discussed with respect to the trade-off between power reduction, performance degradation, and system level constraints. A complete top-down design flow is demonstrated for power gating techniques introducing new design methodologies for the switch sizing task and circuit blocks for data-retention and block activation. The leakage reduction ratio and the minimum power-down time are introduced as figures of merit to describe the power gating technique on system level and give a relation to physical circuit parameters. Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies mainly deals with circuit design but also addresses the interface between circuit and system level design on the one side and between circuit and physical design on the other side.