Andere Kunden interessierten sich auch für
![Analog Layout Synthesis]( "Analog Layout Synthesis")
Analog Layout Synthesis110,99 €![Low-Power Variation-Tolerant Design in Nanometer Silicon]( "Low-Power Variation-Tolerant Design in Nanometer Silicon")
Low-Power Variation-Tolerant Design in Nanometer Silicon74,99 €![Hardware Acceleration of Eda Algorithms]( "Hardware Acceleration of Eda Algorithms")
Hardware Acceleration of Eda Algorithms74,99 €![On and Off-Chip Crosstalk Avoidance in VLSI Design]( "On and Off-Chip Crosstalk Avoidance in VLSI Design")
On and Off-Chip Crosstalk Avoidance in VLSI Design110,99 €![Analysis and Design of Resilient VLSI Circuits]( "Analysis and Design of Resilient VLSI Circuits")
Analysis and Design of Resilient VLSI Circuits110,99 €![Minimizing and Exploiting Leakage in VLSI Design]( "Minimizing and Exploiting Leakage in VLSI Design")
Minimizing and Exploiting Leakage in VLSI Design111,99 €![ESL Models and their Application]( "ESL Models and their Application")
ESL Models and their Application82,99 €
This book presents new concepts, techniques and promising programming models for designing software for chips with "many" (hundreds to thousands) processor cores. Given the scale of parallelism inherent to these chips, software designers face new challenges in terms of operating systems, middleware and applications. This will serve as an invaluable, single-source reference to the state-of-the-art in programming many-core chips. Coverage includes many-core architectures, operating systems, middleware, and programming models.