Realization of Memory Fault Tolerance using Error Correcting Codes - S. Murti Sarma, N.;Lavanya, Poluboyina;Prasad Acharya, Gobinda
32,99 €
inkl. MwSt.
Versandkostenfrei*
Versandfertig in 6-10 Tagen
  • Broschiertes Buch

This work is aimed towards the implementation of a fault-tolerant memory system with the help of supporting circuits. This work demonstrates an improvement on the reliability of a semiconductor memory system using Error control codes (ECC)and Low Density Parity Check (LDPC) Codes as a part of protecting support logic. It is observed that the error correcting codes with higher hamming distances can detect more errors i.e. as higher the hamming distance higher the error control capability.

Andere Kunden interessierten sich auch für
Produktbeschreibung
This work is aimed towards the implementation of a fault-tolerant memory system with the help of supporting circuits. This work demonstrates an improvement on the reliability of a semiconductor memory system using Error control codes (ECC)and Low Density Parity Check (LDPC) Codes as a part of protecting support logic. It is observed that the error correcting codes with higher hamming distances can detect more errors i.e. as higher the hamming distance higher the error control capability.
Autorenporträt
N.S.Murti Sarma is a professor of Electronics and communications Engineering of Hosting College. P.Pradeep is identifed as a successful graduate research scholar by research assessment committee . Dr.S.P.Venumadhavarao is director of R&D of SNIST, Hyderabad.