Vikram Arkalgud Chandrasetty (Principal Engineer, ASIC Design, West, Syed Mahfuzul Aziz (Electrical Professor and Electronic Engineerin

Resource Efficient Ldpc Decoders

From Algorithms to Hardware Architectures

• Broschiertes Buch

Produktbeschreibung

This book takes a practical hands-on approach to developing low complexity algorithms and transforming them into working hardware. It follows a complete design approach - from algorithms to hardware architectures - and addresses some of the challenges associated with their design, providing insight into implementing innovative architectures based on low complexity algorithms. The reader will learn: * Modern techniques to design, model and analyze low complexity LDPC algorithms as well as their hardware implementation * How to reduce computational complexity and power consumption using computer aided design techniques * All aspects of the design spectrum from algorithms to hardware implementation and performance trade-offs

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Produktdetails

• Verlag: Elsevier Science Publishing Co Inc
• Seitenzahl: 190
• Erscheinungstermin: 5. Dezember 2017
• Englisch
• Abmessung: 193mm x 234mm x 16mm
• Gewicht: 426g
• ISBN-13: 9780128112557
• ISBN-10: 0128112557
• Artikelnr.: 48097266

Autorenporträt

Vikram Chandrasetty received Bachelor Degree in Electronics and Communication Engineering from Bangalore University (INDIA), Master Degree in VLSI System Design from Coventry University (UK) and PhD in Computer Systems Engineering from the University of South Australia (Australia). During his post-doctoral research fellowship at the University of New Castle (Australia) he worked on designing spatially coupled LDPC codes and hardware implementations. He reviews articles for many journals including Elsevier and IEEE Transactions. Vikram also has substantial experience as a professional engineer. He has worked on ASIC/FPGA design, error correction coding, electronic design automation, cryptography and communication systems for renowned companies including Motorola and SanDisk. He is currently working on designing memory controllers for next generation storage products in Western Digital.

Inhaltsangabe

1. Introduction2. Overview of LDPC codes3. Structure and flexibility of
LDPC codes4. LDPC decoding algorithms5. LDPC decoder architectures6.
Hardware implementation of LDPC decoder7. LDPC decoders in multimedia
communication8. Prospective LDPC applications
AppendixA : Sample C-Programs and MATLAB models for LDPC code construction
and simulationB : Sample Verilog HDL codes for implementation of
fully-parallel LDPC decoder architectureC : Sample Verilog HDL codes for
implementation of partially-parallel LDPC decoder architecture