Babu, Hafiz M, H,

Reversible and DNA Computing

• Gebundenes Buch

Produktbeschreibung

Master the subjects of reversible computing and DNA computing with this expert volume

Reversible and DNA Computing offers readers new ideas and technologies in the rapidly developing field of reversible computing. World-renowned researcher and author Hafiz Md. Hasan Babu shows readers the fundamental concepts and ideas necessary to understand reversible computing, including reversible circuits, reversible fault tolerant circuits, and reversible DNA circuits.

Reversible and DNA Computing contains a practical approach to understanding energy-efficient DNA computing. In addition to explaining the foundations of reversible circuits, the book covers topics including:
_ Advanced logic design
_ An introduction to the fundamentals of reversible computing
_ Advanced reversible logic synthesis
_ Reversible fault tolerance
_ Fundamentals of DNA computing
_ Reversible DNA logic synthesis
_ DNA logic design

This book is perfect for undergraduate and graduate students in the physical sciences and engineering, as well as those working in the field of quantum computing. It belongs on the bookshelves of anyone with even a passing interest in nanotechnology, energy-efficient computing, and DNA computing.

Produktdetails

• Verlag: Wiley / Wiley & Sons
• Artikelnr. des Verlages: 1W119679420
• 1. Auflage
• Seitenzahl: 432
• Erscheinungstermin: 9. November 2020
• Englisch
• Abmessung: 246mm x 173mm x 30mm
• Gewicht: 907g
• ISBN-13: 9781119679424
• ISBN-10: 1119679427
• Artikelnr.: 58777874

Autorenporträt

HAFIZ MD. HASAN BABU is the Pro-Vice-Chancellor of National University in Bangladesh. He received his M.Sc degree in computer science and engineering from the Brno University of Technology in the Czech Republic in 1992. He has written over 100 research articles for reputable international journals.

Inhaltsangabe

List of Figures xvii

List of Tables xxix

About the Author xxxi

Preface xxxiii

Acknowledgments xxxv

Acronyms xxxvii

Introduction xxxix

Part I Reversible Circuits 1

An Overview About Reversible Circuits 1

1 Reversible Logic Synthesis 5

1.1 Reversible Logic 5

1.2 Reversible Function 5

1.3 Reversible Logic Gate 6

1.4 Garbage Outputs 6

1.5 Constant Inputs 7

1.6 Quantum Cost 7

1.7 Delay 8

1.8 Power 8

1.9 Area 8

1.10 Hardware Complexity 9

1.11 Quantum Gate Calculation Complexity 9

1.12 Fan-Out 10

1.13 Self-Reversible 10

1.14 Reversible Computation 10

1.15 Area 11

1.16 Design Constraints for Reversible Logic Circuits 11

1.17 Quantum Analysis of Different Reversible Logic Gates 12

1.17.1 Reversible NOT Gate (Feynman Gate) 12

1.17.2 Toffoli Gate 12

1.17.3 Fredkin Gate 13

1.17.4 Peres Gate 13

1.18 Summary 13

2 Reversible Adder and Subtractor Circuits 15

2.1 Reversible Multi-Operand n-Digit Decimal Adder 15

2.1.1 Full Adder 15

2.1.2 Carry Skip Adder 19

2.1.2.1 Design of Carry Skip Adder 20

2.1.3 Carry Look-Ahead Adder 24

2.2 Reversible BCD Adders 26

2.2.1 Design Procedure of the Reversible BCD Adder 27

2.2.1.1 Properties of the Reversible BCD Adder 28

2.2.2 Design Procedure of the Reversible Carry Skip BCD Adder 31

2.2.2.1 Properties of the Reversible Carry Skip BCD Adder 32

2.3 Reversible BCD Subtractor 34

2.3.1 Carry Look-Ahead BCD Subtractor 36

2.3.2 Carry Skip BCD Subtractor 36

2.3.3 Design of Conventional Reversible BCD Subtractor 37

2.3.3.1 Reversible Nine's Complement 37

2.3.3.2 Reversible BCD Subtractor 38

2.3.3.3 Reversible Design of Carry Look-Ahead BCD Subtractor 40

2.3.3.4 Reversible Design of Carry Skip BCD Subtractor 40

2.4 Summary 41

3 Reversible Multiplier Circuit 43

3.1 Multiplication Using Booth's Recoding 43

3.2 Reversible Gates as Half Adders and Full Adders 44

3.3 Some Signed Reversible Multipliers 45

3.4 Design of Reversible Multiplier Circuit 45

3.4.1 Some Quantum Gates 46

3.4.2 Recoding Cell 46

3.4.3 Partial Product Generation Circuit 49

3.4.4 Multi-Operand Addition Circuit 52

3.4.5 Calculation of Area and Power of n × n Multiplier Circuit 52

3.5 Summary 64

4 Reversible Division Circuit 67

4.1 The Division Approaches 67

4.1.1 Restoring Division 67

4.1.2 Nonrestoring Division 67

4.2 Components of Division Circuit 68

4.2.1 Reversible MUX 68

4.2.2 Reversible Register 68

4.2.3 Reversible PIPO Left-Shift Register 68

4.2.4 Reversible Parallel Adder 70

4.3 The Design of Reversible Division Circuit 71

4.4 Summary 74

5 Reversible Binary Comparator 75

5.1 Design of Reversible n-Bit Comparator 75

5.1.1 BJS Gate 75

5.1.2 Reversible 1-Bit Comparator Circuit 76

5.1.3 Reversible MSB Comparator Circuit 77

5.1.4 Reversible Single-Bit Greater or Equal Comparator Cell 78

5.1.5 Reversible Single-Bit Less Than Comparator Cell 79

5.1.6 Reversible 2-Bit Comparator Circuit 79

5.1.7 Reversible n-Bit Comparator Circuit 79

5.2 Summary 85

6 Reversible Sequential Circuits