Shared Hardware Accelerator for Hybrid AHt-MPSoC Architecture - Prasath, R. Arun;Maheswari, P. Uma
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In this system, there is presented a new class of hybrid AHt-MPSoC architecture in which hardware accelerators are shared between processors in such a way that to reduce system cost and increase performance. A novel hybrid memory scheme is proposed by this scheme is assessed through extensive simulation to show significant improvements in performance. Hybrid Asymmetric heterogeneous MPSoC architecture consists of a Static Random Access Memory (SRAM) and an embedded Dynamic Random Access Memory (eDRAM) cell in association to Hardware Accelerator (HWA) shared methodology to determine the common…mehr

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Produktbeschreibung
In this system, there is presented a new class of hybrid AHt-MPSoC architecture in which hardware accelerators are shared between processors in such a way that to reduce system cost and increase performance. A novel hybrid memory scheme is proposed by this scheme is assessed through extensive simulation to show significant improvements in performance. Hybrid Asymmetric heterogeneous MPSoC architecture consists of a Static Random Access Memory (SRAM) and an embedded Dynamic Random Access Memory (eDRAM) cell in association to Hardware Accelerator (HWA) shared methodology to determine the common computational tasks in between the concurrent tasks of application. An experimental result shows that the proposed hybrid AHt-MPSoC system power consumption reduced from the existing system and their area/performance tradeoffs evaluated very quickly.
Autorenporträt
Dr. R. Arun Prasath, Professor in der Abteilung für ECE am Siddhartha Institute of Technology & Science, Telangana. Er erhielt seinen Doktortitel in ICE von der Anna University, Chennai. Er verfügt über mehr als 10 Jahre Erfahrung sowohl in der Lehre als auch in der Forschung. Seine Forschungsinteressen umfassen VLSI-Signalverarbeitung, Lowpower VLSI und drahtlose Sensornetzwerke.