Raminderpal Singh (Hrsg.)

Signal Integrity Effects in Custom IC and ASIC Designs

Herausgegeben:Singh, Raminderpal

• Gebundenes Buch

Produktbeschreibung

Dieses Buch hilft Ihnen bei der Lösung spezieller Probleme beim Design von kundenspezifischen integrierten Schaltkreisen und ASICs. Behandelt werden u.a. verschiedene Einflüsse auf die Signalintegrität für hochleistungsfähige Hochfrequenzschaltungen, ASIC-Designs bei Strukturbreiten von 0,18 Mikrometern und integrierte Custom-IC-Blocks in ASIC-Designs.

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Produktdetails

• Verlag: IEEE Press / Wiley & Sons
• 1. Auflage
• Seitenzahl: 480
• Erscheinungstermin: 12. Dezember 2001
• Englisch
• Abmessung: 288mm x 221mm x 26mm
• Gewicht: 1260g
• ISBN-13: 9780471150428
• ISBN-10: 0471150428
• Artikelnr.: 10255193

Autorenporträt

RAMINDERPAL SINGH, PhD, is a signal integrity expert working for IBM's Design Kits Group. He has spent many years developing solutions for substrate noise and coupling, as well as ASIC signal integrity.

Inhaltsangabe

Foreword.
From the Early Days of CMOS to Today.
Signal Integrity: A Problem for Design and CAD Engineers.
Preface.
Acknowledgments.
Signal Integrity Effects in Systme-on-Chip Designs - A Designer's
Perspective.
Part 1: Interconnect Crosstalk.
Harmony: Static Noise Analysis of Deep Submicron Digital Integrated
Circuits.
FastCap: A Multipole Accelerated 3-D Capacitance Extraction Program.
Efficient Coupled Noise Estimation for On-Chip Interconnects.
Switching Window Computation for Static Timing Analysis in Presence of
Crosstalk Noise.
Digital Sensitivity: Predicting Signal Interaction using Functional
Analysis.
Crosstalk Reduction for VLSI.
Noise-aware Repeater Insertion and Wire Sizing For On-Chip Interconnect
Hierarchical Moment-Matching.
Post Global Routing Crosstalk Synthesis.
Minimum Crosstalk Channel Routing.
Reducing Cross-Coupling among Interconnect Wires in Deep-Submicron Datapath
Design.
A Postprocessing Algorithm for Crosstalk-driven Wire Perturbation.
Noise in Digital Dynamic CMOS Circuits.
Design of Dynamic Circuits with Enhanced Noise Tolerance.
Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design.
High Frequency Simulation and Characterization of Advanced Copper
Interconnects.
Static Noise Analysis for Digital Integrated Circuits in Partially-Depleted
Silicon-On-Insulator Technology.
Synthesis of CMOS Domino Circuits for Charge Sharing Alleviation.
Part 2: Inductance Effects.
On-Chip Wiring Design Challenges for Gigahertz Operation.
IC Analyses Including Extracted Inductance Models.
FASTHENRY: A Multipole-Accelerated 3-D Inductance Extraction Program.
Full-Chip, Three-Dimensional, Shapes-Based RLC Extraction.
On-Chip Inductance Modeling and Analysis.
How to Efficiently Capture On-Chip Inductance Effects: Introducing a New
Circuit Element K.
Figures of Merit to Characterize the Importance of On-Chip Inductance.
Layout-Techniques for Minimizing On-Chip Interconnect Self Inductance.
A Twisted-Bundle Layout Structure for Minimizing Inductive Coupling Noise.
Part 3: Power Grid and Distribution Noise.
Full-Chip Verification of UDSM Designs.
Power Supply Noise in Future IC's: A Crystal Ball Reading.
A Floorplan-based Planning Methodology for Power and Clock Distribution in
ASICs.
Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip
Design.
Analysis of Performance Impact Caused by Power Supply Noise in Deep
Submicron Devices.
Full-Chip Signal Interconnect Analysis for Electromigration Reliability.
Power Dissipation Analysis and Optimization of Deep Submicron CMOS Digital
Circuits.
Simulation and Optimization of the Power Distribution Network in VLSI
Circuits.
Design Strategies and Decoupling Techniques for Reducing the Effects of
Electrical Interference in Mixed-Mode IC's.
Design and Analysis of Power Distribution Networks in Power PC
Microprocessors.
Modeling the Power and Ground Effects of BGA Packages.
Effects of Power/Ground Via Distribution on the Power/Ground Performance of
C4/BGA Packages.
Power Distribution Fidelity of Wirebond Compared to Flip Chip Devices in
Grid Array Packages.
Forming Damped LRC Parasitic Circuits in Simultaneously Switched CMOS
Output Buffers.
Part 4: Substrate Noise.
Experimental Results and Modeling Techniques for Substrate Noise in
Mixed-Signal Integrated Circuits.
Principles of Substrate Crosstalk Generation in CMOS Circuits.
Experimental Comparison of Substrate Noise Coupling Using Different Wafer
Types.
Modeling and Analysis of Substrate Coupling in Integrated Circuits.
Fast Methods for Extraction and Sparsification of Substrate Coupling.
SUBWAVE: A Methodology for Modeling Digital Substrate Noise Injection in
Mixed-Signal ICs.
Substrate Modeling and Lumped Substrate Resistance Extraction for CMOS
ESD/Latchup Circuit Simulation.
Analysis of Ground-Bounce Induced Substrate Noise Coupling in a Low
Resistive Bulk Epitaxial Process: Design Strategies to Minimize Noise
Effects on a Mixed-Signal Chip.
A Methodology for Measurement and Characterization of Substrate Noise in
High Frequency Circuits.
Measurement of Digital Noise in Mixed-Signal Integrated Circuits.
Effects of Substrate Resistances on LNA Performance and a Bondpad Structure
for Reducing the Effects in a Silicon Bipolar Technology.
A Study of Oscillator Jitter Due to Supply and Substrate Noise.
CMOS Technology Characterization for Analog and RF Design.
Noise Reduction Is Crucial to Mixed-Signal ASIC Design Success (Parts I &
II).
Author Index.
Subject Index.
About the Editor.

Rezensionen

"In the era of System-on-Chip, when large portions of the overall system are integrated on one large chip, designers are facing increasingly challenging issues. For the first time, this book is taking a closer look at the signal integrity problems faced by both high-performance and cost-performance applications, digital and mixed-signal integrated circuits. System designers are given guidance in power distribution analysis, interconnect optimization, and mixed, digital-analog circuit integration challenges. Researchers and CAD engineers can get an in-depth view of the current and future requirements for full-chip CAD tools, on-chip transmission line designs, integrated passive components, and many other critical signal integrity issues. This book is bringing together a broad range of representative papers that will further the understanding both in the industrial and academic communities."
(Alina Deutsch, Research Staff Member, T.J. Watson Research Center, International Business Machines)
"Electrical integrity (or environment noise) is becoming the principal obstacle in system-on-a-chip design. Digital circuits create a very noisy environment in which other digital and analog circuits must function. This environmental noise comes about because of coupling through the interconnect, power supply, and substrate. This book surveys the latest literature on electrical integrity analysis and design and is, therefore, an invaluable resource for anyone designing systems-on-a-chip."
(Kenneth L. Shepard, Professor, Columbia University)
"The explosion of wireless communications that offer greater mobility and broadband communications that provide super fast access to the Internet have placed new demands on IC designers. The key to developing successful Systems on Chip designs that offer Analog and Mixed Signal capabilities is the approach used to extract and analyze the affects of parasitics on signal integrity. This book offers a tutorial guide to IC designers who want to move to the next level of chip design by unlocking the secrets of signal integrity."
(Jake Buurma Senior Vice President, Worldwide Research & Development, Cadence Design Systems, Inc.)
"As technology scales to .1 micron and below, second order effects due to physical phenomena that were not much visible before start playing a more and more significant role. So much so that well-established methodologies and tools are not providing the necessary level of confidence to the designer that her/his integrated circuit will perform as planned. The need for more accurate extraction and analysis is obvious when we observe horror stories about very hard to detect intermittent faults created by interactions among signals on different wires. There are two complementary approaches to the problem that come to mind as always when we go over the limit of previous methods - increase the accuracy of the analysis tools, and/or solve the problems by imposing constraints on the degrees of freedom left to the designer. This collection of papers covers both in details. It is the most comprehensive syllabus of important results for researchers and designers on the topic. I highly recommend to read it and to pay attention to the messages given by the papers of the collection."
(Alberto Sangiovanni-Vincentelli, Professor, University of California Berkeley)