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Practical realization of low-power, high-speed transistor technologies for future generation nano- electronics can be achieved with novel structures, such as FinFET, tri-gate or with the integration of exotic channel materials,such as Gallium Nitride (GaN), into Fully-Depleted SOI(FDSOI) transistor architectures. Novel Structures are the most promising candidates for logic devices with sub-20nm gate length. They can increase gate control and suppress short channel effects. To compare the feasibility of these different structures and to project the device performance, technology CAD (TCAD)…mehr

Produktbeschreibung
Practical realization of low-power, high-speed
transistor technologies for future generation nano-
electronics can be achieved with novel structures,
such as FinFET, tri-gate or with the integration of
exotic channel materials,such as Gallium Nitride
(GaN), into Fully-Depleted SOI(FDSOI) transistor
architectures.
Novel Structures are the most promising candidates
for logic devices with sub-20nm gate length. They
can increase gate control and suppress short channel
effects. To compare the feasibility of these
different structures and to project the device
performance, technology CAD (TCAD) simulation is a
reasonable method.
The III-V semiconductors, such as Gallium Nitride
(GaN), have high maximum electron drift velocities
and ballistic mean free paths, which would enable
high-speed transistor operation at very low voltages
with gate lengths below 10nm. Since it s impractical
for experiments currently, TCAD simulation can be
used to project performance goals for aggressively
scaled devices.
This research focus on the methodology to compare
different technologies for alternative
to Silicon based traditional logic device using TCAD
simulations.
Autorenporträt
Yawei Jin was born in 1979.He got his PhD from North Carolina
State University in 2006.His work focuses on simulation and
modeling of nano-scale logic devices including novel structure
and III-nitride based devices for alternative to
tranditional MOSFET.He also worked as intern in Micro&Nano
Structure Technology Lab at GE Research in 2005.