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This book presents the detailed design and implementation of an FPGA-based image and video co- processor. Central to this environment is a hierarchical library of efficient hardware architectures for image and video applications, and a Prolog-based hardware description notation called HIDE. The environment also includes a high level generator which takes image processing high level algorithm descriptions based on the abstractions of image algebra and translates automatically into a HIDE hardware description. The latter is then automatically translated into low level FPGA hardware in EDIF netlist format. Central to the satisfaction of the dual requirement of high level design and low level hardware efficiency is the novel concept of hardware skeletons, which act as a bridge between the two levels. These are reusable architectural frameworks, which can take function blocks and possibly other skeletons as parameters while encapsulating all of the low level hardware dependent optimisations. This is illustrated in this book through a real hardware implementation on a commercial FPGA board.