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Dynamic Partial Reconfiguration (DPR) is a hybrid software-hardware computer structure, which combines the software flexibility and hardware efficiency. The DPR technique is employed in a proposed novel design for implementing different communication chains using an adaptable single chain. This work shows the advantages of using DPR feature of the FPGA in the implementation of Software Defined Radio (SDR) System that can switch among different communication standards such as 2G, 3G, LTE, and WIFI. The SDR system is being hardware reconfigured run-time to simulate Multi-band / Multi-standard…mehr

Produktbeschreibung
Dynamic Partial Reconfiguration (DPR) is a hybrid software-hardware computer structure, which combines the software flexibility and hardware efficiency. The DPR technique is employed in a proposed novel design for implementing different communication chains using an adaptable single chain. This work shows the advantages of using DPR feature of the FPGA in the implementation of Software Defined Radio (SDR) System that can switch among different communication standards such as 2G, 3G, LTE, and WIFI. The SDR system is being hardware reconfigured run-time to simulate Multi-band / Multi-standard wireless communication systems, where the reconfiguration is being held on FPGA partially and dynamically, while the FPGA is fully functioning. The results show an improvement in area and power consumption.
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Autorenporträt
Ahmad Sadek received the B.Sc. and M.Sc. degrees in Electronics and Communications Engineering from Cairo University, Cairo, Egypt in 2005 and 2016 respectively. He has several years of experience in Software Development, Embedded Systems, FPGA, System-on-Chip and Wireless Communications. He worked for Honeywell Inc., Intel Corp. and Synopsys Inc.