Structural design simulation of Advanced High Performance Bus protocol
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Currently the problems in the industries due to the lack of proper data transferring between the IP cores on the System on Chip (SOC) system. In recent days, the development of SOC chips and the reusable IP cores are given higher priority because of its less cost and reduction in the period of Time-to-Market. So this enables the major and very sensitive issue such as interfacing of these IP cores. These interfaces play a vital role in SOC and should be taken care because of the communication between the IP cores property. The communication between the different IP cores should have a lossless ...
Currently the problems in the industries due to the lack of proper data transferring between the IP cores on the System on Chip (SOC) system. In recent days, the development of SOC chips and the reusable IP cores are given higher priority because of its less cost and reduction in the period of Time-to-Market. So this enables the major and very sensitive issue such as interfacing of these IP cores. These interfaces play a vital role in SOC and should be taken care because of the communication between the IP cores property. The communication between the different IP cores should have a lossless data flow and should be flexible to the designer too. Hence to resolve this issue, the standard protocol buses are used in or order to interface the two IP cores. Here the loss of data depends on the standards of protocols used. Most of the IP cores from ARM uses the AMBA (Advanced Micro controller Bus Architecture) which has AHB (Advanced High-Performance Bus). This bus has its own advantages and flexibility. A full AHB interface is used for Bus masters, On-chip memory blocks, External memory interfaces, High-bandwidth peripherals with FIFO interfaces and DMA slave peripherals.
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