Subthreshold behavior enhancement of GaN MESFET
For high speed digital applications
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As technology scaling is pushing device dimensions into sub-0.1 µm regime, short channel effects and reliability issues have become areas of severe concern. Since conventional gate oxide thickness scaling gives rise to higher gate leakage, alternative approaches such as the use of gate engineering to alleviate these concerns will be a critical part of device design. The continuous downscaling of FET-based technology has made it attractive for system-on-chip applications, where the analog circuits are realized with the digital systems in the same integrated circuit to reduce the cost and impro...
As technology scaling is pushing device dimensions into sub-0.1 µm regime, short channel effects and reliability issues have become areas of severe concern. Since conventional gate oxide thickness scaling gives rise to higher gate leakage, alternative approaches such as the use of gate engineering to alleviate these concerns will be a critical part of device design. The continuous downscaling of FET-based technology has made it attractive for system-on-chip applications, where the analog circuits are realized with the digital systems in the same integrated circuit to reduce the cost and improve the performance. But conventional FET-based technology is facing greater challenges in terms of scaling due to reduced gate control, increased short-channel effects (SCEs) and high leakage currents. New designs, approaches and techniques are required to overcome these effects and limitations in order to improve the electrical performance for Large Scale Circuit Integration (LSCI) applications.
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