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Increasing the complexity of the electronic systems
leads to electronic system level modeling concept
supporting hardware and software co-design and
co-verification environment in a single framework.
SystemC, an IEEE approved electronic design
standard for system design and verification
processes, provides such an environment by supporting
a wide range of abstraction levels from system-level
to register-transfer level. In this book, two
different models of a processor core, whose
instruction set architecture is compatible with
TI MSP430 microcontroller, are designed by
employing the classical hardware modeling capability
of the SystemC. With its well-designed orthogonal
instruction set, elegant addressing modes, useful
constant generators and flexible von-Neumann
architecture, 16-bit RISC-like processor of the
MSP430 microcontroller is an ideal selection for the
SoC designs. Instruction set and addressing modes of
the designed processors are simulated thoroughly.
Moreover, original CRC programs are used to verify
the processor cores. SystemC to
hardware flow is also illustrated by synthesizing the
ALU part of the processor into a Xilinx-based
hardware.
leads to electronic system level modeling concept
supporting hardware and software co-design and
co-verification environment in a single framework.
SystemC, an IEEE approved electronic design
standard for system design and verification
processes, provides such an environment by supporting
a wide range of abstraction levels from system-level
to register-transfer level. In this book, two
different models of a processor core, whose
instruction set architecture is compatible with
TI MSP430 microcontroller, are designed by
employing the classical hardware modeling capability
of the SystemC. With its well-designed orthogonal
instruction set, elegant addressing modes, useful
constant generators and flexible von-Neumann
architecture, 16-bit RISC-like processor of the
MSP430 microcontroller is an ideal selection for the
SoC designs. Instruction set and addressing modes of
the designed processors are simulated thoroughly.
Moreover, original CRC programs are used to verify
the processor cores. SystemC to
hardware flow is also illustrated by synthesizing the
ALU part of the processor into a Xilinx-based
hardware.