Technology Mapping for Lookup-Table Based FPGAs - Kao, Chi-Chou
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The increasing popularity of the field programmable gate array (FPGA) technology has generated a great deal of interest in the algorithmic study and tool development for FPGA specific design automation problems. The most widely used FPGAs are LUT based FPGAs, in which the basic logic element is a k-input lookup table (LUT) that can implement any Boolean function of up to k variables. This unique feature of the LUT has brought new challenges to technology mapping. This book studies the technology mapping problem for LUT-based FPGAs. According to the experimental results, the proposed algorithm generates favorable results for various FPGA architectures.…mehr

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Produktbeschreibung
The increasing popularity of the field programmable gate array (FPGA) technology has generated a great deal of interest in the algorithmic study and tool development for FPGA specific design automation problems. The most widely used FPGAs are LUT based FPGAs, in which the basic logic element is a k-input lookup table (LUT) that can implement any Boolean function of up to k variables. This unique feature of the LUT has brought new challenges to technology mapping. This book studies the technology mapping problem for LUT-based FPGAs. According to the experimental results, the proposed algorithm generates favorable results for various FPGA architectures.
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Autorenporträt
Chi-Chou Kao received a PhD degrees in electrical engineering from National Cheng-Kung University, Taiwan, in 2002. He is currently a Professor in the Department of Computer Science and Information Engineering, National University of Tainan, Taiwan.