N. K Jha, S. Gupta

Testing of Digital Systems

• Gebundenes Buch

Produktbeschreibung

Device testing represents the single largest manufacturing expense in the semiconductor industry, costing over $40 billion a year. The most comprehensive and wide ranging book of its kind, Testing of Digital Systems covers everything you need to know about this vitally important subject. Starting right from the basics, the authors take the reader through automatic test pattern generation, design for testability and built-in self-test of digital circuits before moving on to more advanced topics such as IDDQ testing, functional testing, delay fault testing, memory testing, and fault diagnosis. The book includes detailed treatment of the latest techniques including test generation for various fault models, discussion of testing techniques at different levels of integrated circuit hierarchy and a chapter on system-on-a-chip test synthesis. Written for students and engineers, it is both an excellent senior/graduate level textbook and a valuable reference.

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Produktdetails

• Verlag: Cambridge University Press
• Seitenzahl: 1018
• Erscheinungstermin: 21. Dezember 2017
• Englisch
• Abmessung: 250mm x 175mm x 58mm
• Gewicht: 1897g
• ISBN-13: 9780521773560
• ISBN-10: 0521773563
• Artikelnr.: 22225119

Autorenporträt

Niraj Jha is Professor of Electrical Engineering at Princeton University and head of the Center of Embedded System-on-a-Chip Design, where his current research is focussed on the synthesis and testing of these devices. He is a fellow of IEEE, associate editor of IEEE Transactions on VLSI Systems and The Journal of Electronic Testing: Theory and Applications (JETTA) and a recipient of the AT&T Foundation award and the NEC preceptorship award for research excellence.

Inhaltsangabe

1. Introduction
2. Fault models
3. Combinational logic and fault simulation
4. Test generation for combinational circuits
5. Sequential ATPG
6. IDDQ testing
7. Functional testing
8. Delay fault testing
9. CMOS testing
10. Fault diagnosis
11. Design for testability
12. Built-in self-test
13. Synthesis for testability
14. Memory testing
15. High-level test synthesis
16. System-on-a-chip testing
Index.