Testing Sequence Dependent Defects - Devta-Prasanna, Narendra
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With new technologies that continue to shrink the feature size of integrated circuits into deep sub-micron domain, there is an increasingly higher incidence of sequence dependent defects during manufacturing. Two-pattern tests are therefore being used in manufacturing testing to supplement the traditional method of single pattern tests based on the stuck-at fault model. In this work we present methods of generating and applying two-pattern test sets to enable high quality and cost effective testing of sequence dependent defects such as transition delay faults, transistor stuck-open faults etc.

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Produktbeschreibung
With new technologies that continue to shrink the feature size of integrated circuits into deep sub-micron domain, there is an increasingly higher incidence of sequence dependent defects during manufacturing. Two-pattern tests are therefore being used in manufacturing testing to supplement the traditional method of single pattern tests based on the stuck-at fault model. In this work we present methods of generating and applying two-pattern test sets to enable high quality and cost effective testing of sequence dependent defects such as transition delay faults, transistor stuck-open faults etc.
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Autorenporträt
Narendra Devta-Prasanna, PhD; Obtained PhD from University of Iowa and bachelors from Indian Institute of Technology, Roorkee;Specializes in DFT techniques for test cost reduction and test quality improvement; Previously worked as VLSI Design Engineer at MindTree Technologies and is currently working as Staff Engineer at LSI Corporation.