Andere Kunden interessierten sich auch für
![ROI Framework for Generic Handwritten Amharic Form]( "ROI Framework for Generic Handwritten Amharic Form")
ROI Framework for Generic Handwritten Amharic Form32,99 €![Generic Software Distribution and Deployment]( "Generic Software Distribution and Deployment")
Generic Software Distribution and Deployment32,99 €![A Generic Framework for Medical Image Segmentation]( "A Generic Framework for Medical Image Segmentation")
A Generic Framework for Medical Image Segmentation32,99 €![Generic Architecture]( "Generic Architecture")
Generic Architecture45,99 €![A generic architecture for e Government and e Democracy]( "A generic architecture for e Government and e Democracy")
A generic architecture for e Government and e Democracy51,99 €![Heuristics & Phylogenies]( "Heuristics & Phylogenies")
Heuristics & Phylogenies20,99 €![A Generic Natural Language Processing Tool for Odiya]( "A Generic Natural Language Processing Tool for Odiya")
A Generic Natural Language Processing Tool for Odiya36,99 €
Due to increased time-to-market constraints,
development of systems composed of new hardand
software becomes more and more challenging. Software
development needs to start at a time
when hardware is still under development and
therefore needs to be simulated on general purpose
workstations. If the hardware to be simulated is a
parallel system composed of both hard- and
software, powerful simulation tools are needed in
order to be useful for effective development.
With the Generic Simulation Framework, clock-cycle
accurate simulation for parallel devices
communicating with each other is possible. The tool
presented in this work is designed to support
different model techniques at various levels of
abstraction (even inside the same simulation run)
and is currently used for verification and
design-space exploration in the design process of a
parallel processor system. By adding hierarchical
levels reflecting the physical structure of the
simulation, and using certain synchronization
algorithms, a speedup is tried to be achieved.
development of systems composed of new hardand
software becomes more and more challenging. Software
development needs to start at a time
when hardware is still under development and
therefore needs to be simulated on general purpose
workstations. If the hardware to be simulated is a
parallel system composed of both hard- and
software, powerful simulation tools are needed in
order to be useful for effective development.
With the Generic Simulation Framework, clock-cycle
accurate simulation for parallel devices
communicating with each other is possible. The tool
presented in this work is designed to support
different model techniques at various levels of
abstraction (even inside the same simulation run)
and is currently used for verification and
design-space exploration in the design process of a
parallel processor system. By adding hierarchical
levels reflecting the physical structure of the
simulation, and using certain synchronization
algorithms, a speedup is tried to be achieved.