The Gm/Id Methodology, a Sizing Tool for Low-Voltage Analog CMOS Circuits
The Semi-Empirical and Compact Model Approaches
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The gm/ID Methodology, a Sizing Tool for Low-Voltage Analog CMOS Circuits compares the semi-empirical method to a compact model driven approach. The few parameters required by the compact model are attractive for they pave the way towards analytic expressions unaffordable with advanced tools like BSIM or PSP. The E.K.V model is a good contender for it reproduces the modes of operation of MOS transistors in a continuous manner with few representations. However when it comes to short channel devices, it looses straightforwardness. Since the methodology requires essentially a reliable large signal representation of the MOS transistor, we investigate the potential of the E.K.V model when its parameters are bias dependent. The method is compared to the semi-empirical sizing approach considering the Intrinsic Gain Stage and the basic Miller Op. Amp. A series of MATLAB files is provided to assess the performances of the compact model gm/ID sizing methodology.
In "The gm/ID Methodology, a Sizing Tool for Low-Voltage Analog CMOS Circuits", we compare the semi-empirical to the compact model approach. Small numbers of parameters make the compact model attractive for the model paves the way towards analytic expressions unaffordable otherwise. The E.K.V model is a good candidate, but when it comes to short channel devices, compact models are either inaccurate or loose straightforwardness. Because sizing requires basically a reliable large signal representation of MOS transistors, we investigate the potential of the E.K.V model when its parameters are supposed to be bias dependent. The model-driven and semi-empirical methods are compared considering the Intrinsic Gain Stage and a few more complex circuits. A series of MATLAB files found on extras-springer.com allow redoing the tests.
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