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The development of computing performance faced different limitations. The "memory wall" limited the performance from the beginning. For today the single processor performance has hit the "complexity wall" and "thermal wall". The computing approached and reached the final limits the laws of the nature enable. The practical need for increasing the computing performance (large amount of computing operations and data, the growing interest in deploying artificial intelligence; all these in real-time) gave more focus to parallelization. The discussion in this booklet scrutinizes whether the present…mehr

Produktbeschreibung
The development of computing performance faced different limitations. The "memory wall" limited the performance from the beginning. For today the single processor performance has hit the "complexity wall" and "thermal wall". The computing approached and reached the final limits the laws of the nature enable. The practical need for increasing the computing performance (large amount of computing operations and data, the growing interest in deploying artificial intelligence; all these in real-time) gave more focus to parallelization. The discussion in this booklet scrutinizes whether the present efforts to produce high-performance systems from a very large number of parallelized sequential processors can be successful. A new limitation: the "performance wall" is faced, which originates from the very basics of the computing: the computing paradigm and its clock-driven electronic implementation. This finding has far-reaching consequences. The book explains the sometimes shocking unexpected saturation limitations and failures in fields like building exa-scale supercomputers, running exa-scale programs, or simulating the operation of the human brain.
Autorenporträt
The author has started his carrier as research physicist using informatics and more than a decade ago switched to researching informatics where he became full professor. His main research topic is the efficacy of computation, including mainly non-conventional and parallelized implementations.