The VAMP Memory Unit

The VAMP Memory Unit

Hardware Design and Formal Verification

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This work is devoted to the formal verification ofthe VAMP memory unit (MU) and based on the workcarried out in [Dal06]. The new design of the MU,developed here, contains translation look-asidebuffers (TLB) for fast virtual address translationinside the memory management units (MMU) and supportsaccesses to external devices.A computer-aided verification tool used throughoutthe whole work is an interactive theorem proverIsabelle/HOL bound [Tve05] with the NuSMV [CCG+02]and SMV [McM99] model checkers. The results(correctness proofs and models of hardware blocks)are presented as Isabelle mathemati...