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This book provides the reader with a complete understanding of why three dimensional IC design is a promising solution to continue performance scaling, the possible ways to do 3D integration (fabrication), the EDA challenges and solutions to facilitate designers to do 3D IC design, the architectural benefits of using 3D technology, and the design issues at the architecture level.
The work covers the background on 3D integration, fabrication options for 3D ICs, EDA flows and algorithms for 3D design, architecture level design techniques for 3D microarchitecture. The book includes an introduction on the background of 3D IC, a motivation that explains why the 3D IC is important and how it will trend, 3D process (fabrication) options, 3D EDA algorithms and tools (physical level and architectural level tools), 3D microarchitecture, including 3D FPGA, 3D single core/multi core processors, 3D Network-onchip designs.
We live in a time of great change. In the electronics world, the last several decades have seen unprecedented growth and advancement, described by Moore's law. This observation stated that transistor density in integrated circuits doubles every 1. 5-2 years. This came with the simultaneous improvement of individual device perf- mance as well as the reduction of device power such that the total power of the resulting ICs remained under control. No trend remains constant forever, and this is unfortunately the case with Moore's law. The trouble began a number of years ago when CMOS devices were no longer able to proceed along the classical scaling trends. Key device parameters such as gate oxide thickness were simply no longer able to scale. As a result, device o- state currents began to creep up at an alarming rate. These continuing problems with classical scaling have led to a leveling off of IC clock speeds to the range of several GHz. Of course, chips can be clocked higher but the thermal issues become unmanageable. This has led to the recent trend toward microprocessors with mul- ple cores, each running at a few GHz at the most. The goal is to continue improving performance via parallelism by adding more and more cores instead of increasing speed. The challenge here is to ensure that general purpose codes can be ef?ciently parallelized. There is another potential solution to the problem of how to improve CMOS technology performance: three-dimensional integrated circuits (3D ICs).
The work covers the background on 3D integration, fabrication options for 3D ICs, EDA flows and algorithms for 3D design, architecture level design techniques for 3D microarchitecture. The book includes an introduction on the background of 3D IC, a motivation that explains why the 3D IC is important and how it will trend, 3D process (fabrication) options, 3D EDA algorithms and tools (physical level and architectural level tools), 3D microarchitecture, including 3D FPGA, 3D single core/multi core processors, 3D Network-onchip designs.
We live in a time of great change. In the electronics world, the last several decades have seen unprecedented growth and advancement, described by Moore's law. This observation stated that transistor density in integrated circuits doubles every 1. 5-2 years. This came with the simultaneous improvement of individual device perf- mance as well as the reduction of device power such that the total power of the resulting ICs remained under control. No trend remains constant forever, and this is unfortunately the case with Moore's law. The trouble began a number of years ago when CMOS devices were no longer able to proceed along the classical scaling trends. Key device parameters such as gate oxide thickness were simply no longer able to scale. As a result, device o- state currents began to creep up at an alarming rate. These continuing problems with classical scaling have led to a leveling off of IC clock speeds to the range of several GHz. Of course, chips can be clocked higher but the thermal issues become unmanageable. This has led to the recent trend toward microprocessors with mul- ple cores, each running at a few GHz at the most. The goal is to continue improving performance via parallelism by adding more and more cores instead of increasing speed. The challenge here is to ensure that general purpose codes can be ef?ciently parallelized. There is another potential solution to the problem of how to improve CMOS technology performance: three-dimensional integrated circuits (3D ICs).