Vasilis F. Pavlidis, Ioannis Savidis, Eby G. Friedman

Three-Dimensional Integrated Circuit Design

• Broschiertes Buch

Produktbeschreibung

Three-Dimensional Integrated Circuit Design, Second Eition, expands the original with more than twice as much new content, adding the latest developments in circuit models, temperature considerations, power management, memory issues, and heterogeneous integration. 3-D IC experts Pavlidis, Savidis, and Friedman cover the full product development cycle throughout the book, emphasizing not only physical design, but also algorithms and system-level considerations to increase speed while conserving energy. A handy, comprehensive reference or a practical design guide, this book provides effective solutions to specific challenging problems concerning the design of three-dimensional integrated circuits.

Expanded with new chapters and updates throughout based on the latest research in 3-D integration:

Manufacturing techniques for 3-D ICs with TSVs Electrical modeling and closed-form expressions of through silicon vias Substrate noise coupling in heterogeneous 3-DICs Design of 3-D ICs with inductive links Synchronization in 3-D ICs Variation effects on 3-D ICs Correlation of WID variations for intra-tier buffers and wires

Offers practical guidance on designing 3-D heterogeneous systems Provides power delivery of 3-D ICs Demonstrates the use of 3-D ICs within heterogeneous systems that include a variety of materials, devices, processors, GPU-CPU integration, and more Provides experimental case studies in power delivery, synchronization, and thermal characterization

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Produktdetails

• Verlag: Morgan Kaufmann
• Artikelnr. des Verlages: 65307483
• 2. Aufl.
• Seitenzahl: 768
• Erscheinungstermin: 3. Juli 2017
• Englisch
• Abmessung: 236mm x 195mm x 43mm
• Gewicht: 1578g
• ISBN-13: 9780124105010
• ISBN-10: 0124105017
• Artikelnr.: 47793569

Autorenporträt

Vasilis F. Pavlidis received the B.Sc. and M.Eng. degrees in Electrical and Computer Engineering from the Democritus University of Thrace, Greece, in 2000 and 2002, respectively. He received the M.Sc. and Ph.D. degrees in Electrical and Computer Engineering from the University of Rochester, Rochester, NY, in 2003 and 2008, respectively. He is currently an Assistant Professor in the School of Computer Science at the University of Manchester, Manchester, UK. From 2008 to 2012, he was a post-doctoral fellow with the Integrated Systems Laboratory at the Ecole Polytechnique Fédérale de Lausanne, Lausanne, Switzerland. He was with INTRACOM S.A., Athens, Greece, from 2000 to 2002. He has also been a visiting researcher at Synopsys Inc., Mountain View, CA, with the Primetime group in 2007. His current research interests include interconnect modeling and analysis, 3-D and 2.5-D integration, and other issues related to VLSI design. He has published several conference and journal papers in these areas. He was the leading designer of the Rochester cube and co-creator of the Manchester Thermal Analyzer. Dr. Pavlidis is on the editorial board of the Microelectronics Journal and Integration, the VLSI Journal. He also serves on the Technical Program Committees of several IEEE conferences. He is a member of the VLSI Systems & Applications Technical Committee of the Circuits and Systems Society and a member of the IEEE. He is also involved in public policy issues as a member of the ICT working group of the IEEE European Public Policy Initiative.

Inhaltsangabe

1. Introduction 2. Manufacturing of 3-D Packaged Systems 3. 3-D Integrated Circuit Fabrication Technologies 4. Electrical Modeling and Closed-Form Expressions of Through Silicon Vias 5. Substrate Noise Coupling in Heterogeneous 3-D ICs 6. Design of 3-D ICs with Inductive Links 7. Interconnect Prediction Models 8. Cost Issues for 3-D Integrated Systems 9. Physical Design Techniques for 3-D ICs 10. Timing Optimization for Two-Terminal Interconnects 11. Timing Optimization for Multi-Terminal Interconnects 12. Thermal Modeling and Analysis 13. Thermal Management Strategies for 3-D ICs 14. Case Study: Thermal Effects in a prototype 3-D IC 15. Three-Dimensional Networks-on-Chip 16. Synchronization in 3-D ICs 17. Case Study: Clock distribution in 3-D ICs 18. Variation Effects on 3-D ICs 19. Power Delivery and Distribution for 3-D ICs 20. Case Study: Power Distribution Networks in 3-D ICs 21. Conclusions and Future Prospects

Appendix A: Enumeration of Gate Pairs in a 3-D IC B: Formal Proof of Optimum Single Via Placement C: Proof of the Two-Terminal Via Placement Heuristic D: Proof of Condition for Via Placement of Multi-Terminal Nets Glossary E: Correlation of WID Variations for Intra-Tier Buffers F: Extension of the Proposed Model to Include Variations of Wires