Simon Louwsma, Ed van Tuijl, Bram Nauta

Time-Interleaved Analog-To-Digital Converters

• Gebundenes Buch

Produktbeschreibung

This book describes the design of a high performance time-interleaved ADC, with much attention given to practical design aspects aimed at both industry and research. There is focus on low-power design techniques including successive approximation ADCs.

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Time-interleaved Analog-to-Digital Converters describes the research performed on low-power time-interleaved ADCs. A detailed theoretical analysis is made of the time-interleaved Track & Hold, since it must be capable of handling signals in the GHz range with little distortion, and minimal power consumption. Timing calibration is not attractive, therefore design techniques are presented which do not require timing calibration.

The design of power efficient sub-ADCs is addressed with a theoretical analysis of a successive approximation converter and a pipeline converter. It turns out that the first can consume about 10 times less power than the latter, and this conclusion is supported by literature.

Time-interleaved Analog-to-Digital Converters describes the design of a high performance time-interleaved ADC, with much attention for practical design aspects, aiming at both industry and research. Measurements show best-inclass performance with a sample-rate of 1.8 GS/s, 7.9 ENOBs and a power efficiency of 1 pJ/conversion-step.

Produktdetails

• Analog Circuits and Signal Processing
• Verlag: Springer / Springer Netherlands
• Artikelnr. des Verlages: 80016325, 978-90-481-9715-6
• 2011 edition
• Seitenzahl: 136
• Erscheinungstermin: 18. September 2010
• Englisch
• Abmessung: 244mm x 163mm x 18mm
• Gewicht: 372g
• ISBN-13: 9789048197156
• ISBN-10: 9048197155
• Artikelnr.: 30578227

Inhaltsangabe

1. Introduction. - 2. Time-interleaved Track and Holds.- 3. Sub-ADC architectures for time-interleaved ADCs. - 4. Implementation of a high-speed time-interleaved ADC. - 5. Summary and conclusions.

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1. Introduction. – 2. Time-interleaved Track and Holds.- 3. Sub-ADC architectures for time-interleaved ADCs. – 4. Implementation of a high-speed time-interleaved ADC. – 5. Summary and conclusions.