Ivan S. Kourtev, Baris Taskin, Eby G. Friedman

Timing Optimization Through Clock Skew Scheduling

• Broschiertes Buch

Produktbeschreibung

This book details timing analysis and optimization techniques for circuits with level-sensitive memory elements. It contains a linear programming formulation applicable to the timing analysis of large scale circuits and includes a delay insertion methodology that improves the efficiency of clock skew scheduling. Coverage also provides a framework for and results from implementing timing optimization algorithms in a parallel computing environment.

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History of the Book The last three decades have witnessed an explosive development in - tegrated circuit fabrication technologies. The complexities of current CMOS circuits are reaching beyond the 65 nanometer feature size and multi-hundred million transistors per integrated circuit. To fully exploit this technological potential, circuit designers use sophisticated Computer-Aided Design (CAD) tools. While supporting the talents of innumerable microelectronics engineers, these CAD tools have become the enabling factor responsible for the succe- ful design and implementation of thousands of high performance, large scale integrated circuits. This book (a research monograph) originated from a body of doctoral d- sertationresearchcompletedbythe?rstauthorattheUniversityofRochester from 1994 to 1999 while under the supervision of Prof. Eby G. Friedman. This research focuses on issues in the design of the clock distribution network in large scale, high performance digital synchronous circuits and particularly, on algorithmsfornon-zero clockskewscheduling.Duringthedevelopmentofthis research, it became clear that incorporating timing issues into the successful integrated circuit design process is of fundamental importance, particularly in that advanced theoretical developments in this area have been slow to reach the designers' desktops. The second edition of the book is enhanced by the body of doctoral dissertation research completed by the second author at the University of Pittsburgh from 2000 to 2005 under the supervision of Prof.

Produktdetails

• Verlag: Springer / Springer US / Springer, Berlin
• Artikelnr. des Verlages: 978-1-4419-4377-4
• Softcover reprint of hardcover 1st ed. 2009
• Seitenzahl: 284
• Erscheinungstermin: 4. November 2010
• Englisch
• Abmessung: 235mm x 155mm x 16mm
• Gewicht: 434g
• ISBN-13: 9781441943774
• ISBN-10: 1441943773
• Artikelnr.: 32654474

Autorenporträt

The focus of this book is on timing analysis and optimization techniques for circuits with level-sensitive memory elements (registers). Level-sensitive registers are becoming significantly more popular in practice as integrated circuit densities are increasing and the performance-per-power metric for integrated circuits becomes a key issue. Therefore, techniques for understanding level-sensitive based circuits and for optimizing the performance of such circuits are increasingly important. The book contains a linear programming formulation applicable to the timing analysis of large scale circuits. It includes a delay insertion methodology, and offers an overview of circuit partitioning, placement, and synchronization methodologies that enables the implementation of high speed, low power circuits synchronized with ultra-modern resonant clocking technology.

Inhaltsangabe

VLSI Systems.- Signal Delay in VLSI Systems.- Timing Properties of Synchronous Systems.- Clock Skew Scheduling and Clock Tree Synthesis.- Clock Skew Scheduling of Level-Sensitive Circuits.- Clock Skew Scheduling for Improved Reliability.- Delay Insertion and Clock Skew Scheduling.- Practical Considerations.- Clock Skew Scheduling in Rotary Clocking Technology.- Experimental Results.