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Many digital signal processing and communication
algorithms are first simulated using floating-point
arithmetic and are later transformed into fixed-point
arithmetic to reduce implementation
complexity. This transformation process may take
most of the design time for complex designs and may
involve a long series of manual ad-hoc design
choices. This book provides methods to find optimum
word lengths efficiently, implement low-power
fixed-point arithmetic by word length reduction
techniques, and automate the transformation process
from floating-point to fixed-point arithmetic. The
automation step provides a design tradeoff curve of
signal quality vs. implementation complexity for the
system, which allows the designer to pick any
operating point on the tradeoff curve. The book
should help in developing fixed-point hardware or
software implementations from floating-point
representations, and should be especially useful to
professionals who are developing high-speed or
low-power hardware or software.
algorithms are first simulated using floating-point
arithmetic and are later transformed into fixed-point
arithmetic to reduce implementation
complexity. This transformation process may take
most of the design time for complex designs and may
involve a long series of manual ad-hoc design
choices. This book provides methods to find optimum
word lengths efficiently, implement low-power
fixed-point arithmetic by word length reduction
techniques, and automate the transformation process
from floating-point to fixed-point arithmetic. The
automation step provides a design tradeoff curve of
signal quality vs. implementation complexity for the
system, which allows the designer to pick any
operating point on the tradeoff curve. The book
should help in developing fixed-point hardware or
software implementations from floating-point
representations, and should be especially useful to
professionals who are developing high-speed or
low-power hardware or software.