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Two wideband balun-LNA configurations have been designed in 65nm COMS technology. Both of them employ a single-to-differential (S-to-D) conversion topology composed of a common gate (CG) stage and a common source (CS) stage, providing output balancing and noise and distortion cancelling. One is inductorless and the other one exploits gain-boosting current-balancing topology. In addition, the sensitivity of IIP2 is deeply investigated. Balun-LNA I/Q-mixers, which combine the balun-LNA cores and double-balanced mixers, are also designed in the same CMOS technology to resolve the bandwidth…mehr

Produktbeschreibung
Two wideband balun-LNA configurations have been designed in 65nm COMS technology. Both of them employ a single-to-differential (S-to-D) conversion topology composed of a common gate (CG) stage and a common source (CS) stage, providing output balancing and noise and distortion cancelling. One is inductorless and the other one exploits gain-boosting current-balancing topology. In addition, the sensitivity of IIP2 is deeply investigated. Balun-LNA I/Q-mixers, which combine the balun-LNA cores and double-balanced mixers, are also designed in the same CMOS technology to resolve the bandwidth limitation in traditional direct-conversion receivers. With 2.5V supply, around 20dB conversion gain, 3dB DSB noise figure, 18.3dB IIP2 and -3dB IIP3 are obtained by the BLIXER using LNA.A over the bandwidth of 0.5 to 8GHz, while consuming 29mW DC power. The counterpart, the BLIXER using LNA.B, achieves around 20dB conversion gain, 4dB DSB noise figure, 38dB IIP2 and 2.8dB IIP3 over the same bandwidth while dissipating 15mW from 2.5/1.8V supplies.
Autorenporträt
Lin Zhu received the M.S degree in SOC from Lund University, Lund, Sweden, in 2012. He has been working with Montage Technology since 2012. His most recent activity at Montage is in the area of data communication and mixed signal IC design, e.g., Ethernet PHY and SERDES I/Os.