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Power consumption is becoming worse with every technology generation. While there has been much research in recent years proposing design methods addressing this issue, one of the most efficient approaches is to reduce supply voltage. In our research, we found the optimal voltage (Vmin) for energy efficiency in CMOS technology. We analyzed the different factors affecting Vmin and find that Vmin usually lies in subthreshold voltage regime. To verify the high energy efficiency of subthreshold operation, we designed and fabricated two subthreshold processors in 0.13um technology, specifically, the Subliminal 1 and Subliminal 2 processors. Measurements confirm 2.60pJ per instruction efficiency for the Subliminal 1. Also, we designed and fabricated the first sub-200mV compact 6-T SRAM in a commercial 0.13um CMOS technology. Silicon measurements show that all 24 dies measured were fully functional and a typical die operates from 1.2V to 193mV. Then to address the lost performance from voltage scaling, we proposed a novel micro-architecture and found that having multiple cores sharing one faster local L1 provides the best energy efficiency.