Shanthi Pavan, Richard Schreier, Gabor C. Temes

Understanding Delta-SIGMA Data Converters

• Gebundenes Buch

Produktbeschreibung

This new edition introduces operation and design techniques for Sigma-Delta converters in physical and conceptual terms, and includes chapters which explore developments in the field over the last decade
_ Includes information on MASH architectures, digital-to-analog converter (DAC) mismatch and mismatch shaping
_ Investigates new topics including continuous-time DeltaSigma analog-to-digital converters (ADCs) principles and designs, circuit design for both continuous-time and discrete-time DeltaSigma ADCs, decimation and interpolation filters, and incremental ADCs
_ Provides emphasis on practical design issues for industry professionals

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Produktdetails

• IEEE Press Series on Microelectronic Systems
• Verlag: Wiley & Sons / Wiley-IEEE Press
• Artikelnr. des Verlages: 1W119258270
• 2. Aufl.
• Seitenzahl: 592
• Erscheinungstermin: 24. Januar 2017
• Englisch
• Abmessung: 243mm x 164mm x 33mm
• Gewicht: 1012g
• ISBN-13: 9781119258278
• ISBN-10: 1119258278
• Artikelnr.: 47616322

Autorenporträt

Shanthi Pavan is a Professor of electrical engineering at the Indian Institute of Technology, India, and has been the Editor-In-Chief of the IEEE Transactions on Circuits and Systems, and a Distinguished Lecturer of the IEEE Solid State Circuits Society.  He is a Fellow of the Indian National Academy of Engineering. Richard Schreier was a Division Fellow in Analog Devices Inc. and an Adjunct Professor at the University of Toronto, Canada, when he retired in 2016. From 1991-1997 he was a Professor at Oregon State University.He was named an IEEE Fellow in 2015. Gabor Temes is a Distinguished Professor Emeritus of the University of California, and Professor in the School of Electrical Engineering and Computer Science at Oregon State University, USA.  He is an IEEE Life Fellow and a member of the US National Academy of Engineering.

Inhaltsangabe

Preface xiii

1 The Magic of Delta-Sigma Modulation 1

1.1 The Need for Oversampling Converters 1

1.2 Nyquist and Oversampling Conversion by Example 3

1.3 Higher-Order Single-Stage Noise-Shaping Modulators 11

1.4 Multi-Stage and Multi-Quantizer Delta-Sigma Modulators 12

1.5 Mismatch Shaping in Multi-Bit Delta-Sigma Modulators 14

1.6 Continuous-Time Delta-Sigma Modulation 15

1.7 Bandpass Delta-Sigma Modulators 17

1.8 Incremental Delta-Sigma Converters 18

1.9 Delta-Sigma Digital-to-Analog Converters 18

1.10 Decimation and Interpolation 19

1.11 Specifications and Figures of Merit 19

1.12 Early History, Performance, and Architectural Trends 21

References 25

2 Sampling, Oversampling, and Noise-Shaping 27

2.1 A Review of Sampling 28

2.2 Quantization 30

2.3 Quantization Noise Reduction by Oversampling 39

2.4 Noise-Shaping 42

2.5 Nonlinear Aspects of the First-Order Delta-Sigma Modulator 52

2.6 MOD1 with DC Excitation 54

2.7 Alternative Architectures: The Error-Feedback Structure 60

2.8 The Road Ahead 60

References 61

3 Second-Order Delta-Sigma Modulation 63

3.1 Simulation of MOD2 67

3.2 Nonlinear Effects in MOD2 70

3.3 Stability of MOD2 73

3.4 Alternative Second-Order Modulator Structures 77

3.5 Generalized Second-Order Structures 80

3.6 Conclusions 82

References 82

4 High-Order Delta-Sigma Modulators 83

4.1 Signal-Dependent Stability of Delta-Sigma Modulators 85

4.2 Improving MSA in High-Order Delta-Sigma Converters 92

4.3 Systematic NTF Design 95

4.4 Noise Transfer Functions with Optimally Spread Zeros 97

4.5 Fundamental Aspects of Noise Transfer Functions 98

4.6 High-Order Single-Bit Delta-Sigma Data Converters 100

4.7 Loop Filter Topologies for Discrete-Time Delta-Sigma Converters 104

4.8 State-Space Description of Delta-Sigma Loops 114

4.9 Conclusions 115

References 115

5 Multi-Stage and Multi-Quantizer Delta-Sigma Modulators 117

5.1 Multi-Stage Modulators 117

5.2 Cascade (MASH) Modulators 120

5.3 Noise Leakage in Cascade Modulators 123

5.4 The Sturdy-MASH Architecture 126

5.5 Noise-Coupled Architectures 128

5.6 Cross-Coupled Architectures 131

5.7 Conclusions 131

References 133

6 Mismatch-Shaping 135

6.1 The Mismatch Problem 135

6.2 Random Selection and Rotation 136

6.3 Implementation of Rotation 141

6.4 Alternative Mismatch-Shaping Topologies 145

6.5 High-Order Mismatch-Shaping 151

6.6 Generalizations 156

6.7 Transition-Error Shaping 158

6.8 Conclusions 162

References 162

7 Circuit Design for Discrete-Time Delta-Sigma ADCs 165

7.1 SCMOD2: A Second-Order Switched-Capacitor ADC 165

7.2 High-Level Design 166

7.3 Switched-Capacitor Integrator 168

7.4 Capacitor Sizing 174

7.5 Initial Verification 176

7.6 Amplifier Design 178

7.7 Intermediate Verification 186

7.8 Switch Design 191

7.9 Comparator Design 191

7.10 Clocking 195

7.11 Full-System Verification 197

7.12 High-Order Modulators 201

7.13 Multi-Bit Quantization 203

7.14 Switch Design Revisited 207

7.15 Double Sampling 209

7.16 Gain-Boosting and Gain-Squaring 211