UNIFICATION OF VLSI PARTITIONING - Adya, Saurabh
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As VLSI circuits become larger and more complex, the need to improve design automation tools becomes more urgent. Interconnect effects dominate performance and power in the Deep Submicron regime, and Computer Aided Design tools and methodologies need to focus more on interconnect optimization. In addition, there is a push for dramatic levels of on-chip integration in modern circuits. The cumulative effects of the two make design of leading-edge electronic products difficult. In this work, we propose improved techniques and methodologies for layout design of modern VLSI chips. These techniques…mehr

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Produktbeschreibung
As VLSI circuits become larger and more complex, the need to improve design automation tools becomes more urgent. Interconnect effects dominate performance and power in the Deep Submicron regime, and Computer Aided Design tools and methodologies need to focus more on interconnect optimization. In addition, there is a push for dramatic levels of on-chip integration in modern circuits. The cumulative effects of the two make design of leading-edge electronic products difficult. In this work, we propose improved techniques and methodologies for layout design of modern VLSI chips. These techniques can be classified as floorplanning, mixed-size placement and VLSI placement for physical synthesis. The proposed algorithms address novel problem formulations and design concerns that arise in modern VLSI designs.
Autorenporträt
Saurabh Adya received the B.E. degree in E&C from NITK, Surathkal, India, in 1999, and M.S./Ph.D degrees in CSE from University of Michigan, Ann Arbor, in 2002/2004. He has worked professionally as a R&D engineer at Texas Instruments, Synplicity, Synopsys and Magma. His research interests are in advancing state of the art in VLSI CAD.