Ben Cohen

VHDL Coding Styles and Methodologies

• Gebundenes Buch

Produktbeschreibung

VHDL Coding Styles and Methodologies provides an in-depth study of the VHDL language rules, coding styles, and methodologies. This book clearly distinguishes good from poor coding methodologies using an easy to remember symbology notation along with a rationale for each guideline. The VHDL concepts, rules and styles are demonstrated using complete compilable and simulatable examples which are also supplied on the accompanying disk. VHDL Coding Styles and Methodologies provides practical applications of VHDL and techniques that are current in the industry. It explains how to apply the VHDL guidelines using several complete examples. The `learning by example' teaching approach along with an in-depth presentation of the language rules application methodology provides the necessary knowledge to create digital hardware designs and models that are readable, maintainable, predictable, and efficient. VHDL Coding Styles and Methodologies is intended for both college students and design engineers. It provides a practical approach to learning VHDL. Combining methodologies and coding styles along with VHDL rules leads the reader in the right direction from the beginning.

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Hinweis: Dieser Artikel kann nur an eine deutsche Lieferadresse ausgeliefert werden.

Produktdetails

• Verlag: Springer
• Seitenzahl: 392
• Erscheinungstermin: 31. August 1995
• Englisch
• Abmessung: 260mm x 183mm x 27mm
• Gewicht: 932g
• ISBN-13: 9780792395980
• ISBN-10: 0792395980
• Artikelnr.: 37200317

Inhaltsangabe

Preface. About the Disk. Notation Conventions. 1. VHDL Overview and
Concepts. 2. Basic Language Elements. 3. Control Structures. 4. Drivers. 5.
VHDL Timing. 6. Elements of Entity/Architecture. 7. Subprograms. 8.
Packages. 9. User Defined Attributes, Specifications, and Configurations.
10. Functional Models and Testbenches. 11. UART Project. 12. Vital. 13.
Design for Synthesis. Appendix A: VHDL'93 and VHDL'87 Syntax Summary.
Appendix B: Package Standard. Appendix C: Package Textio. Appendix D:
Package STD_Logic_1164. Appendix E: VHDL Preferred Attributes. Index.

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Vhdl Overview and Concepts.- Basic Language Elements.- Control Structures.- Drivers.- Vhdl Timing.- Elements of Entity/Architecture.- Subprograms.- Packages.- User Defined Attributes, Specifications, and Configurations.- Design for Synthesis.- Functional Models and Testbenches.- Uart Project.- Vital.