• Produktbild: VLSI Circuits and Embedded Systems
  • Produktbild: VLSI Circuits and Embedded Systems
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VLSI Circuits and Embedded Systems

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Beschreibung

Produktdetails

Einband

Gebundene Ausgabe

Erscheinungsdatum

29.07.2022

Abbildungen

274 SW-Abb., 30 SW-Fotos, 244 SW-Zeichn., 49 Tabellen

Verlag

Taylor & Francis

Seitenzahl

510

Maße (L/B/H)

26/18,3/3,2 cm

Gewicht

1144 g

Sprache

Englisch

ISBN

978-1-03-221608-9

Beschreibung

Produktdetails

Einband

Gebundene Ausgabe

Erscheinungsdatum

29.07.2022

Abbildungen

274 SW-Abb., 30 SW-Fotos, 244 SW-Zeichn., 49 Tabellen

Verlag

Taylor & Francis

Seitenzahl

510

Maße (L/B/H)

26/18,3/3,2 cm

Gewicht

1144 g

Sprache

Englisch

ISBN

978-1-03-221608-9

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  • Produktbild: VLSI Circuits and Embedded Systems
  • Produktbild: VLSI Circuits and Embedded Systems
  • Part-1: Decision Diagrams (DDs)

    Chapter 1: Shared Multi-Terminal Binary Decision Diagrams

    Chapter 2: Multiple-Output Functions

    Chapter 3: Shared Multiple-Valued DDs for Multiple-Output Functions

    Chapter 4: Heuristics to Minimize Multiple-Valued DDs

    Chapter 5: TDM Realizations of Multiple-Output Functions

    Chapter 6: Multiple-Output Switching Functions

    Part-2: An Overview About Design Architectures of Multiple-Valued Circuits

    Chapter 7: Multiple-Valued Flip-Flops using Pass Transistor Logic

    Chapter 8: Voltage-Mode Pass Transistor-based Multi-Valued Multiple-Output Logic Circuits

    Chapter 9: Multiple-Valued Input Binary-Valued Output Functions

    Chapter 10: Digital Fuzzy Operations using Multi-Valued Fredkin Gates

    Chapter 11: Multiple-Valued Multiple-Output Logic Expressions using LUT

    Part-3: Programmable Logic Devices

    Chapter 12: LUT-Based Matrix Multiplication Using Neural Networks

    Chapter 13: Easily Testable PLAs using Pass Transistor Logic

    Chapter 14: Genetic Algorithm for Input Assignment for Decoded-PLAs

    Chapter 15: FPGA-based Multiplier using LUT Merging Theorem

    Chapter 16: Look-Up Table-based Binary Coded Decimal Adder

    Chapter 17: Place and Route Algorithm for Field Programmable Gate Array

    Chapter 18: LUT-based BCD Multiplier Design

    Chapter 19: LUT-based Matrix Multiplier Circuit using Pigeonhole Principle

    Chapter 20: BCD Adder using a LUT-based Field Programmable Gate Array

    Chapter 21: Generic Complex Programmable Logic Device Board

    Chapter 22: FPGA-based Programmable Logic Controller Part-IV: Design Architectures of Advanced Digital Circuits

    Chapter 23: Parallel Computation of Quotients and Partial Remainders to Design Divider Circuits

    Chapter 24: Synthesis of Boolean Functions using TANT Networks

    Chapter 25: Asymmetric High Radix Signed Digital Adder using Neural Networks

    Chapter 26: Wrapper/TAM Co-Optimization and Constrained Test Scheduling for SOCs using Rectangle Bin Packing

    Chapter 27: Static Random Access Memory using Memristor

    Chapter 28: A Fault Tolerant Approach to Microprocessor Design

    Chapter 29: Applications of VLSI Circuits and Embedded Systems