Hafiz Md. Hasan Babu
VLSI Circuits and Embedded Systems
Hafiz Md. Hasan Babu
VLSI Circuits and Embedded Systems
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This book explores the designs of VLSI circuits and embedded systems. As a whole, core researchers, academicians, and students will get the complete picture of VLSI Circuits and Embedded Systems and their applications.
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This book explores the designs of VLSI circuits and embedded systems. As a whole, core researchers, academicians, and students will get the complete picture of VLSI Circuits and Embedded Systems and their applications.
Hinweis: Dieser Artikel kann nur an eine deutsche Lieferadresse ausgeliefert werden.
Hinweis: Dieser Artikel kann nur an eine deutsche Lieferadresse ausgeliefert werden.
Produktdetails
- Produktdetails
- Verlag: Taylor & Francis Ltd
- Seitenzahl: 464
- Erscheinungstermin: 4. Oktober 2024
- Englisch
- Abmessung: 254mm x 178mm x 26mm
- Gewicht: 940g
- ISBN-13: 9781032216102
- ISBN-10: 1032216107
- Artikelnr.: 71582295
- Herstellerkennzeichnung
- Libri GmbH
- Europaallee 1
- 36244 Bad Hersfeld
- 06621 890
- Verlag: Taylor & Francis Ltd
- Seitenzahl: 464
- Erscheinungstermin: 4. Oktober 2024
- Englisch
- Abmessung: 254mm x 178mm x 26mm
- Gewicht: 940g
- ISBN-13: 9781032216102
- ISBN-10: 1032216107
- Artikelnr.: 71582295
- Herstellerkennzeichnung
- Libri GmbH
- Europaallee 1
- 36244 Bad Hersfeld
- 06621 890
Professor Dr. Hafiz Md. Hasan Babu is currently working as a Professor in the Department of Computer Science and Engineering, University of Dhaka, Bangladesh. He is also the former Chairman of the same department. Recently, he has completed his tenured as Pro-Vice-Chancellor of National University, Bangladesh, where he was on deputation from the Department of Computer Science and Engineering, University of Dhaka, Bangladesh. For his excellent academic and administrative capability, he also served as the Professor and founding Chairman of the Department of Robotics and Mechatronics Engineering, University of Dhaka, Bangladesh. He served as a World Bank Senior Consultant and General Manager of the Department of the Information Technology & the Department of Management Information Systems of Janata Bank Limited, Bangladesh. Dr. Hasan Babu was the World Bank Resident Information Technology Expert of the Supreme Court Project Implementation Committee, Supreme Court of Bangladesh. He was also the Information Technology Consultant of Health Economics Unit and the Ministry of Health and Family Welfare in the project "SSK (Shasthyo Shurokhsha Karmasuchi) and Social Health Protection Scheme" under the direct supervision and funding of German Financial Cooperation through KfW.
Part-1: Decision Diagrams (DDs)
Chapter 1: Shared Multi-Terminal Binary Decision Diagrams
Chapter 2: Multiple-Output Functions
Chapter 3: Shared Multiple-Valued DDs for Multiple-Output Functions
Chapter 4: Heuristics to Minimize Multiple-Valued DDs
Chapter 5: TDM Realizations of Multiple-Output Functions
Chapter 6: Multiple-Output Switching Functions
Part-2: An Overview About Design Architectures of Multiple-Valued Circuits
Chapter 7: Multiple-Valued Flip-Flops using Pass Transistor Logic
Chapter 8: Voltage-Mode Pass Transistor-based Multi-Valued Multiple-Output
Logic Circuits
Chapter 9: Multiple-Valued Input Binary-Valued Output Functions
Chapter 10: Digital Fuzzy Operations using Multi-Valued Fredkin Gates
Chapter 11: Multiple-Valued Multiple-Output Logic Expressions using LUT
Part-3: Programmable Logic Devices
Chapter 12: LUT-Based Matrix Multiplication Using Neural Networks
Chapter 13: Easily Testable PLAs using Pass Transistor Logic
Chapter 14: Genetic Algorithm for Input Assignment for Decoded-PLAs
Chapter 15: FPGA-based Multiplier using LUT Merging Theorem
Chapter 16: Look-Up Table-based Binary Coded Decimal Adder
Chapter 17: Place and Route Algorithm for Field Programmable Gate Array
Chapter 18: LUT-based BCD Multiplier Design
Chapter 19: LUT-based Matrix Multiplier Circuit using Pigeonhole Principle
Chapter 20: BCD Adder using a LUT-based Field Programmable Gate Array
Chapter 21: Generic Complex Programmable Logic Device Board
Chapter 22: FPGA-based Programmable Logic Controller Part-IV: Design
Architectures of Advanced Digital Circuits
Chapter 23: Parallel Computation of Quotients and Partial Remainders to
Design Divider Circuits
Chapter 24: Synthesis of Boolean Functions using TANT Networks
Chapter 25: Asymmetric High Radix Signed Digital Adder using Neural
Networks
Chapter 26: Wrapper/TAM Co-Optimization and Constrained Test Scheduling for
SOCs using Rectangle Bin Packing
Chapter 27: Static Random Access Memory using Memristor
Chapter 28: A Fault Tolerant Approach to Microprocessor Design
Chapter 29: Applications of VLSI Circuits and Embedded Systems
Chapter 1: Shared Multi-Terminal Binary Decision Diagrams
Chapter 2: Multiple-Output Functions
Chapter 3: Shared Multiple-Valued DDs for Multiple-Output Functions
Chapter 4: Heuristics to Minimize Multiple-Valued DDs
Chapter 5: TDM Realizations of Multiple-Output Functions
Chapter 6: Multiple-Output Switching Functions
Part-2: An Overview About Design Architectures of Multiple-Valued Circuits
Chapter 7: Multiple-Valued Flip-Flops using Pass Transistor Logic
Chapter 8: Voltage-Mode Pass Transistor-based Multi-Valued Multiple-Output
Logic Circuits
Chapter 9: Multiple-Valued Input Binary-Valued Output Functions
Chapter 10: Digital Fuzzy Operations using Multi-Valued Fredkin Gates
Chapter 11: Multiple-Valued Multiple-Output Logic Expressions using LUT
Part-3: Programmable Logic Devices
Chapter 12: LUT-Based Matrix Multiplication Using Neural Networks
Chapter 13: Easily Testable PLAs using Pass Transistor Logic
Chapter 14: Genetic Algorithm for Input Assignment for Decoded-PLAs
Chapter 15: FPGA-based Multiplier using LUT Merging Theorem
Chapter 16: Look-Up Table-based Binary Coded Decimal Adder
Chapter 17: Place and Route Algorithm for Field Programmable Gate Array
Chapter 18: LUT-based BCD Multiplier Design
Chapter 19: LUT-based Matrix Multiplier Circuit using Pigeonhole Principle
Chapter 20: BCD Adder using a LUT-based Field Programmable Gate Array
Chapter 21: Generic Complex Programmable Logic Device Board
Chapter 22: FPGA-based Programmable Logic Controller Part-IV: Design
Architectures of Advanced Digital Circuits
Chapter 23: Parallel Computation of Quotients and Partial Remainders to
Design Divider Circuits
Chapter 24: Synthesis of Boolean Functions using TANT Networks
Chapter 25: Asymmetric High Radix Signed Digital Adder using Neural
Networks
Chapter 26: Wrapper/TAM Co-Optimization and Constrained Test Scheduling for
SOCs using Rectangle Bin Packing
Chapter 27: Static Random Access Memory using Memristor
Chapter 28: A Fault Tolerant Approach to Microprocessor Design
Chapter 29: Applications of VLSI Circuits and Embedded Systems
Part-1: Decision Diagrams (DDs)
Chapter 1: Shared Multi-Terminal Binary Decision Diagrams
Chapter 2: Multiple-Output Functions
Chapter 3: Shared Multiple-Valued DDs for Multiple-Output Functions
Chapter 4: Heuristics to Minimize Multiple-Valued DDs
Chapter 5: TDM Realizations of Multiple-Output Functions
Chapter 6: Multiple-Output Switching Functions
Part-2: An Overview About Design Architectures of Multiple-Valued Circuits
Chapter 7: Multiple-Valued Flip-Flops using Pass Transistor Logic
Chapter 8: Voltage-Mode Pass Transistor-based Multi-Valued Multiple-Output Logic Circuits
Chapter 9: Multiple-Valued Input Binary-Valued Output Functions
Chapter 10: Digital Fuzzy Operations using Multi-Valued Fredkin Gates
Chapter 11: Multiple-Valued Multiple-Output Logic Expressions using LUT
Part-3: Programmable Logic Devices
Chapter 12: LUT-Based Matrix Multiplication Using Neural Networks
Chapter 13: Easily Testable PLAs using Pass Transistor Logic
Chapter 14: Genetic Algorithm for Input Assignment for Decoded-PLAs
Chapter 15: FPGA-based Multiplier using LUT Merging Theorem
Chapter 16: Look-Up Table-based Binary Coded Decimal Adder
Chapter 17: Place and Route Algorithm for Field Programmable Gate Array
Chapter 18: LUT-based BCD Multiplier Design
Chapter 19: LUT-based Matrix Multiplier Circuit using Pigeonhole Principle
Chapter 20: BCD Adder using a LUT-based Field Programmable Gate Array
Chapter 21: Generic Complex Programmable Logic Device Board
Chapter 22: FPGA-based Programmable Logic Controller Part-IV: Design Architectures of Advanced Digital Circuits
Chapter 23: Parallel Computation of Quotients and Partial Remainders to Design Divider Circuits
Chapter 24: Synthesis of Boolean Functions using TANT Networks
Chapter 25: Asymmetric High Radix Signed Digital Adder using Neural Networks
Chapter 26: Wrapper/TAM Co-Optimization and Constrained Test Scheduling for SOCs using Rectangle Bin Packing
Chapter 27: Static Random Access Memory using Memristor
Chapter 28: A Fault Tolerant Approach to Microprocessor Design
Chapter 29: Applications of VLSI Circuits and Embedded Systems
Chapter 1: Shared Multi-Terminal Binary Decision Diagrams
Chapter 2: Multiple-Output Functions
Chapter 3: Shared Multiple-Valued DDs for Multiple-Output Functions
Chapter 4: Heuristics to Minimize Multiple-Valued DDs
Chapter 5: TDM Realizations of Multiple-Output Functions
Chapter 6: Multiple-Output Switching Functions
Part-2: An Overview About Design Architectures of Multiple-Valued Circuits
Chapter 7: Multiple-Valued Flip-Flops using Pass Transistor Logic
Chapter 8: Voltage-Mode Pass Transistor-based Multi-Valued Multiple-Output Logic Circuits
Chapter 9: Multiple-Valued Input Binary-Valued Output Functions
Chapter 10: Digital Fuzzy Operations using Multi-Valued Fredkin Gates
Chapter 11: Multiple-Valued Multiple-Output Logic Expressions using LUT
Part-3: Programmable Logic Devices
Chapter 12: LUT-Based Matrix Multiplication Using Neural Networks
Chapter 13: Easily Testable PLAs using Pass Transistor Logic
Chapter 14: Genetic Algorithm for Input Assignment for Decoded-PLAs
Chapter 15: FPGA-based Multiplier using LUT Merging Theorem
Chapter 16: Look-Up Table-based Binary Coded Decimal Adder
Chapter 17: Place and Route Algorithm for Field Programmable Gate Array
Chapter 18: LUT-based BCD Multiplier Design
Chapter 19: LUT-based Matrix Multiplier Circuit using Pigeonhole Principle
Chapter 20: BCD Adder using a LUT-based Field Programmable Gate Array
Chapter 21: Generic Complex Programmable Logic Device Board
Chapter 22: FPGA-based Programmable Logic Controller Part-IV: Design Architectures of Advanced Digital Circuits
Chapter 23: Parallel Computation of Quotients and Partial Remainders to Design Divider Circuits
Chapter 24: Synthesis of Boolean Functions using TANT Networks
Chapter 25: Asymmetric High Radix Signed Digital Adder using Neural Networks
Chapter 26: Wrapper/TAM Co-Optimization and Constrained Test Scheduling for SOCs using Rectangle Bin Packing
Chapter 27: Static Random Access Memory using Memristor
Chapter 28: A Fault Tolerant Approach to Microprocessor Design
Chapter 29: Applications of VLSI Circuits and Embedded Systems
Part-1: Decision Diagrams (DDs)
Chapter 1: Shared Multi-Terminal Binary Decision Diagrams
Chapter 2: Multiple-Output Functions
Chapter 3: Shared Multiple-Valued DDs for Multiple-Output Functions
Chapter 4: Heuristics to Minimize Multiple-Valued DDs
Chapter 5: TDM Realizations of Multiple-Output Functions
Chapter 6: Multiple-Output Switching Functions
Part-2: An Overview About Design Architectures of Multiple-Valued Circuits
Chapter 7: Multiple-Valued Flip-Flops using Pass Transistor Logic
Chapter 8: Voltage-Mode Pass Transistor-based Multi-Valued Multiple-Output
Logic Circuits
Chapter 9: Multiple-Valued Input Binary-Valued Output Functions
Chapter 10: Digital Fuzzy Operations using Multi-Valued Fredkin Gates
Chapter 11: Multiple-Valued Multiple-Output Logic Expressions using LUT
Part-3: Programmable Logic Devices
Chapter 12: LUT-Based Matrix Multiplication Using Neural Networks
Chapter 13: Easily Testable PLAs using Pass Transistor Logic
Chapter 14: Genetic Algorithm for Input Assignment for Decoded-PLAs
Chapter 15: FPGA-based Multiplier using LUT Merging Theorem
Chapter 16: Look-Up Table-based Binary Coded Decimal Adder
Chapter 17: Place and Route Algorithm for Field Programmable Gate Array
Chapter 18: LUT-based BCD Multiplier Design
Chapter 19: LUT-based Matrix Multiplier Circuit using Pigeonhole Principle
Chapter 20: BCD Adder using a LUT-based Field Programmable Gate Array
Chapter 21: Generic Complex Programmable Logic Device Board
Chapter 22: FPGA-based Programmable Logic Controller Part-IV: Design
Architectures of Advanced Digital Circuits
Chapter 23: Parallel Computation of Quotients and Partial Remainders to
Design Divider Circuits
Chapter 24: Synthesis of Boolean Functions using TANT Networks
Chapter 25: Asymmetric High Radix Signed Digital Adder using Neural
Networks
Chapter 26: Wrapper/TAM Co-Optimization and Constrained Test Scheduling for
SOCs using Rectangle Bin Packing
Chapter 27: Static Random Access Memory using Memristor
Chapter 28: A Fault Tolerant Approach to Microprocessor Design
Chapter 29: Applications of VLSI Circuits and Embedded Systems
Chapter 1: Shared Multi-Terminal Binary Decision Diagrams
Chapter 2: Multiple-Output Functions
Chapter 3: Shared Multiple-Valued DDs for Multiple-Output Functions
Chapter 4: Heuristics to Minimize Multiple-Valued DDs
Chapter 5: TDM Realizations of Multiple-Output Functions
Chapter 6: Multiple-Output Switching Functions
Part-2: An Overview About Design Architectures of Multiple-Valued Circuits
Chapter 7: Multiple-Valued Flip-Flops using Pass Transistor Logic
Chapter 8: Voltage-Mode Pass Transistor-based Multi-Valued Multiple-Output
Logic Circuits
Chapter 9: Multiple-Valued Input Binary-Valued Output Functions
Chapter 10: Digital Fuzzy Operations using Multi-Valued Fredkin Gates
Chapter 11: Multiple-Valued Multiple-Output Logic Expressions using LUT
Part-3: Programmable Logic Devices
Chapter 12: LUT-Based Matrix Multiplication Using Neural Networks
Chapter 13: Easily Testable PLAs using Pass Transistor Logic
Chapter 14: Genetic Algorithm for Input Assignment for Decoded-PLAs
Chapter 15: FPGA-based Multiplier using LUT Merging Theorem
Chapter 16: Look-Up Table-based Binary Coded Decimal Adder
Chapter 17: Place and Route Algorithm for Field Programmable Gate Array
Chapter 18: LUT-based BCD Multiplier Design
Chapter 19: LUT-based Matrix Multiplier Circuit using Pigeonhole Principle
Chapter 20: BCD Adder using a LUT-based Field Programmable Gate Array
Chapter 21: Generic Complex Programmable Logic Device Board
Chapter 22: FPGA-based Programmable Logic Controller Part-IV: Design
Architectures of Advanced Digital Circuits
Chapter 23: Parallel Computation of Quotients and Partial Remainders to
Design Divider Circuits
Chapter 24: Synthesis of Boolean Functions using TANT Networks
Chapter 25: Asymmetric High Radix Signed Digital Adder using Neural
Networks
Chapter 26: Wrapper/TAM Co-Optimization and Constrained Test Scheduling for
SOCs using Rectangle Bin Packing
Chapter 27: Static Random Access Memory using Memristor
Chapter 28: A Fault Tolerant Approach to Microprocessor Design
Chapter 29: Applications of VLSI Circuits and Embedded Systems
Part-1: Decision Diagrams (DDs)
Chapter 1: Shared Multi-Terminal Binary Decision Diagrams
Chapter 2: Multiple-Output Functions
Chapter 3: Shared Multiple-Valued DDs for Multiple-Output Functions
Chapter 4: Heuristics to Minimize Multiple-Valued DDs
Chapter 5: TDM Realizations of Multiple-Output Functions
Chapter 6: Multiple-Output Switching Functions
Part-2: An Overview About Design Architectures of Multiple-Valued Circuits
Chapter 7: Multiple-Valued Flip-Flops using Pass Transistor Logic
Chapter 8: Voltage-Mode Pass Transistor-based Multi-Valued Multiple-Output Logic Circuits
Chapter 9: Multiple-Valued Input Binary-Valued Output Functions
Chapter 10: Digital Fuzzy Operations using Multi-Valued Fredkin Gates
Chapter 11: Multiple-Valued Multiple-Output Logic Expressions using LUT
Part-3: Programmable Logic Devices
Chapter 12: LUT-Based Matrix Multiplication Using Neural Networks
Chapter 13: Easily Testable PLAs using Pass Transistor Logic
Chapter 14: Genetic Algorithm for Input Assignment for Decoded-PLAs
Chapter 15: FPGA-based Multiplier using LUT Merging Theorem
Chapter 16: Look-Up Table-based Binary Coded Decimal Adder
Chapter 17: Place and Route Algorithm for Field Programmable Gate Array
Chapter 18: LUT-based BCD Multiplier Design
Chapter 19: LUT-based Matrix Multiplier Circuit using Pigeonhole Principle
Chapter 20: BCD Adder using a LUT-based Field Programmable Gate Array
Chapter 21: Generic Complex Programmable Logic Device Board
Chapter 22: FPGA-based Programmable Logic Controller Part-IV: Design Architectures of Advanced Digital Circuits
Chapter 23: Parallel Computation of Quotients and Partial Remainders to Design Divider Circuits
Chapter 24: Synthesis of Boolean Functions using TANT Networks
Chapter 25: Asymmetric High Radix Signed Digital Adder using Neural Networks
Chapter 26: Wrapper/TAM Co-Optimization and Constrained Test Scheduling for SOCs using Rectangle Bin Packing
Chapter 27: Static Random Access Memory using Memristor
Chapter 28: A Fault Tolerant Approach to Microprocessor Design
Chapter 29: Applications of VLSI Circuits and Embedded Systems
Chapter 1: Shared Multi-Terminal Binary Decision Diagrams
Chapter 2: Multiple-Output Functions
Chapter 3: Shared Multiple-Valued DDs for Multiple-Output Functions
Chapter 4: Heuristics to Minimize Multiple-Valued DDs
Chapter 5: TDM Realizations of Multiple-Output Functions
Chapter 6: Multiple-Output Switching Functions
Part-2: An Overview About Design Architectures of Multiple-Valued Circuits
Chapter 7: Multiple-Valued Flip-Flops using Pass Transistor Logic
Chapter 8: Voltage-Mode Pass Transistor-based Multi-Valued Multiple-Output Logic Circuits
Chapter 9: Multiple-Valued Input Binary-Valued Output Functions
Chapter 10: Digital Fuzzy Operations using Multi-Valued Fredkin Gates
Chapter 11: Multiple-Valued Multiple-Output Logic Expressions using LUT
Part-3: Programmable Logic Devices
Chapter 12: LUT-Based Matrix Multiplication Using Neural Networks
Chapter 13: Easily Testable PLAs using Pass Transistor Logic
Chapter 14: Genetic Algorithm for Input Assignment for Decoded-PLAs
Chapter 15: FPGA-based Multiplier using LUT Merging Theorem
Chapter 16: Look-Up Table-based Binary Coded Decimal Adder
Chapter 17: Place and Route Algorithm for Field Programmable Gate Array
Chapter 18: LUT-based BCD Multiplier Design
Chapter 19: LUT-based Matrix Multiplier Circuit using Pigeonhole Principle
Chapter 20: BCD Adder using a LUT-based Field Programmable Gate Array
Chapter 21: Generic Complex Programmable Logic Device Board
Chapter 22: FPGA-based Programmable Logic Controller Part-IV: Design Architectures of Advanced Digital Circuits
Chapter 23: Parallel Computation of Quotients and Partial Remainders to Design Divider Circuits
Chapter 24: Synthesis of Boolean Functions using TANT Networks
Chapter 25: Asymmetric High Radix Signed Digital Adder using Neural Networks
Chapter 26: Wrapper/TAM Co-Optimization and Constrained Test Scheduling for SOCs using Rectangle Bin Packing
Chapter 27: Static Random Access Memory using Memristor
Chapter 28: A Fault Tolerant Approach to Microprocessor Design
Chapter 29: Applications of VLSI Circuits and Embedded Systems