XCore XS1
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Please note that the content of this book primarily consists of articles available from Wikipedia or other free sources online. The XCore XS1 is a 32-bit RISC microprocessor architecture designed by XMOS. The architecture is designed to be used for embedded systems, and instruction encoding is compact using 16 bits for frequently used instructions (with up to three operands) and 32 bits for less frequently used instructions (with up to 6 operands). Almost all instructions execute in a single cycle, and the architecture supports is event driven in order to decouple the timings that a program…mehr

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Please note that the content of this book primarily consists of articles available from Wikipedia or other free sources online. The XCore XS1 is a 32-bit RISC microprocessor architecture designed by XMOS. The architecture is designed to be used for embedded systems, and instruction encoding is compact using 16 bits for frequently used instructions (with up to three operands) and 32 bits for less frequently used instructions (with up to 6 operands). Almost all instructions execute in a single cycle, and the architecture supports is event driven in order to decouple the timings that a program needs to make from the execution speed of the program. A program will normally perform its computations and then wait for an event (eg a message, time, or external I/O event) before continuing. The architecture comprises a central execution unit that operates on a set of 25 registers, a surrounded by a number of _resources_ that perform operations that interact with the environment. Each thread has its own set of hardware registers, enabling threads to execute concurrently.